50.7.2 LCD Voltage Regulator and LCD Output Buffers
The LCD Voltage Regulator is a complete solution to drive an LCD display. It integrates a low-power LDO regulator with programmable output voltage and buffers to drive the LCD lines. A capacitor is required at the LDO regulator output (VDDLCD). This regulator can be set in Active (Normal) mode, in Bypass mode (HiZ mode), or in OFF mode.
- In Normal mode, the VDDLCD LDO regulator output can be selected from 2.4V to 3.5V using LCDVROUT bits in the Supply Controller Mode Register (SUPC_MR), with the conditions:
- VDDLCD ≤ VDD3V3 - 100 mV.
- In Bypass mode (HiZ mode), the VDDLCD is set in high impedance (through the LCDMODE bits in SUPC_MR register), and can be forced externally. This mode can be used to save the LDO operating current.
- In OFF mode, the VDDLCD output is pulled down.
Important: When using an external or the internal voltage
regulator, VDD3V3 must be still supplied with the conditions: 2.4V≤ VDDLCD ≤ VDD3V3 and
VDD3V3 ≥ 2.5V.
| Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| VVDD3V3 | Input supply voltage range | – | 2.5 | 3.6 | V |
| VDDLCD | Programmable output range | Refer to Table 50-19 | V | ||
| VACC | VDDLCD accuracy | With respect to programmed output range | -50 | +50 | mV |
| IVDD3V3 | Current consumption | – | – | 7 | μA |
| COUT | Output capacitor on VDDLCD(1) |
ESR for 1 μF capacitor ESR for 10 μF capacitor |
1 5 1 |
10 20 10 |
μF mΩ mΩ |
| tON | Start-up time(1) | COUT= 1 μF, VDDLCD max | – | 2.5 | ms |
Note:
- Simulation data.
| VROUT | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 12 | 13 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VDDLCD | 2.375 | 2.45 | 2.525 | 2.60 | 2.675 | 2.75 | 2.825 | 2.90 | 2.975 | 3.05 | 3.125 | 3.20 | 3.275 | 3.35 | 3.425 | 3.50 |
| Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| IDDIN | Current consumption (VDD3V3) | Buffered | – | 52 | μA |
|
Unbuffered | – | 5 | |||
| ZOUT | Buffer output impedance(1) | Buffered | 500 | 1300 | Ω |
|
Unbuffered |
300k |
1Meg | |||
| CLOAD | Capacitive output load(1) | – | 10p | 50n | F |
Note:
- Simulation data.
