50.7.2 LCD Voltage Regulator and LCD Output Buffers

The LCD Voltage Regulator is a complete solution to drive an LCD display. It integrates a low-power LDO regulator with programmable output voltage and buffers to drive the LCD lines. A capacitor is required at the LDO regulator output (VDDLCD). This regulator can be set in Active (Normal) mode, in Bypass mode (HiZ mode), or in OFF mode.

  • In Normal mode, the VDDLCD LDO regulator output can be selected from 2.4V to 3.5V using LCDVROUT bits in the Supply Controller Mode Register (SUPC_MR), with the conditions:
    • VDDLCD ≤ VDD3V3 - 100 mV.
  • In Bypass mode (HiZ mode), the VDDLCD is set in high impedance (through the LCDMODE bits in SUPC_MR register), and can be forced externally. This mode can be used to save the LDO operating current.
  • In OFF mode, the VDDLCD output is pulled down.
Important: When using an external or the internal voltage regulator, VDD3V3 must be still supplied with the conditions: 2.4V≤ VDDLCD ≤ VDD3V3 and VDD3V3 ≥ 2.5V.
Table 50-18. LCD Voltage Regulator Characteristics
SymbolParameterConditionsMinMaxUnit
VVDD3V3Input supply voltage range2.53.6V
VDDLCDProgrammable output rangeRefer to Table 50-19V
VACCVDDLCD accuracyWith respect to programmed output range-50+50mV
IVDD3V3Current consumption7μA
COUTOutput capacitor on VDDLCD(1)

ESR for 1 μF capacitor

ESR for 10 μF capacitor

1

5

1

10

20

10

μF

mΩ

mΩ

tONStart-up time(1)COUT= 1 μF, VDDLCD max2.5ms
Note:
  1. Simulation data.
Table 50-19. VDDLCD Voltage Selection at VDD3V3 = 3.6V
VROUT0123456789101112131213
VDDLCD2.3752.452.5252.602.6752.752.8252.902.9753.053.1253.203.2753.353.4253.50
Table 50-20. LCD Analog Buffers Bias Generation Characteristics
SymbolParameterConditionsMinMaxUnit
IDDINCurrent consumption (VDD3V3)Buffered52μA

Unbuffered

5
ZOUTBuffer output impedance(1)Buffered5001300

Unbuffered

300k

1Meg

CLOADCapacitive output load(1)10p50nF
Note:
  1. Simulation data.