7.4.2.3 Routing Recommendation

Following are the routing recommendations for LPDDR4.

• Trace impedance can be 40/80 or 50/100.
• All CA signals and CNTRL signals must length match with CLK.
• DQ/DQS signal must length match.
• Try to make branches short.
• Equal branch length gives better signal integrity performance.
• Reduce the number of VIA on overall DDR lines.
• All DQ/DQS and CLK/CA/Control group signal routing must be similar and transition must be same. For net layer transitions, Microchip recommends routing ground vias next to signal vias for good shielding and to maintain constant impedance.
• Typically, the trunk and the branches are the same impedance. If the branches are kept short, the reflection that returns to the component from the mismatch in impedance between the trunk and branches occurs during the rise time and is not observed as a separate event.
• Slew rate is dependent on the capacitance at the load and the source impedance. The source impedance is the driver impedance plus the transmission line impedance (mostly the trunk). To improve slew rate, consider shading the driver impedance to and the trunk impedance on the low side.
• Ensure that the signals do not cross the split plane and have a reference plane throughout.
• Limit the overall trace length to below two inches.