17.5.11.1 Global Configuration

Update the SFRBU DDR Power Control register (SFRBU_DDRPWR) to take the DDR I/Os out of Retention state.
- Wait for the command to complete by polling bit SFRBU_DDRPWR.RETENTION until it sets to 1.
Update the RSTC Generic Reset register (RSTC_GRSTR) to reset the DDR PHY and DDR controllers.
Perform a dummy read to allow 128 cycles for synchronization.
Update RSTC_GRSTR to release the DDR3PHY reset.
Perform a dummy read to allow 128 cycles for synchronization.

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