17.5.11.5 Step 4

  1. Wait for the DDR3PHY initialization to complete by polling the IDONE bit in the DDR3PHY PHY General Status register (DDR3PHY_PGSR).
  2. In case of re-initialization only: override the ZQ Control impedance calibration by:
    • writing 1 to ZDEN in DDR3PHY ZQ Impedance Control register 0 (DDR3PHY_ZQ0CR0),
    • filling the ZQ impedance field with the previously saved impedance values,
    • restoring data corrupted by the training.