17.5.11.4 Step 3

Update:

  1. DDR3PHY DRAM Configuration register
  2. DDR3PHY PHY General Configuration register
  3. DDR3PHY PHY Timing registers 0 to 2
  4. DDR3PHY Mode registers 0 to 3
  5. DDR3PHY ODT Configuration register
  6. DDR3PHY DRAM Timing Parameters registers 0 to 2
  7. DDR3PHY DDR System General Configuration register
  8. DDR3PHY DATX8 Common Configuration register
  9. DDR3PHY ZQ Impedance Control register 1 (if a DDR2 or DDR3 is being configured)

In case of re-initialization only: bypass the impedance calibration of ZQ control blocks by setting ZCALBYP in the DDR3PHY Initialization register (DDR3PHY_PIR).