17.5.8.2.4 Per-Bank Refresh (LPDDR2/LPDDR3 only)

If RFSHCTL0.per_bank_refresh is set to 1 (see Register Descriptions), the UDDRC performs per-bank refreshes instead of all-bank refreshes. In this case, RFSHTMG.t_rfc_nom_x1_x32 and RFSHTMG.t_rfc_min should be set to the appropriate values for per-bank refresh (tREFIpb and tRFCpb respectively). In this mode, the UDDRC keeps track of which bank is being refreshed at any time, and is able to schedule commands to other banks immediately before and after the per-bank refresh commands, resulting in potential efficiency gains. To improve the accuracy of per-bank refresh timing, set RFSHTMG.t_rfc_nom_x1_sel to 1 and program RFSHTMG.t_rfc_nom_x1_x32 accordingly (see Register Descriptions).

If the refresh burst (RFSHCTL0.refresh_burst) is programmed with a large value in per-bank Refresh mode, and bursting per-bank refreshes start, it may take a longer time than bursting all-bank refreshes. The three possible cases where bursting per-bank refreshes may occur are:

1. Random traffic


   The UDDRC may not be able to issue a speculative refresh because the CAM always has transactions on some banks. This can be avoided with appropriate register settings. For example, setting smaller values to RFSHCTL0.refresh_burst or RFSHCTL0.refresh_to_x1_x32.

2. Toggling RFSHCTL3.refresh_update_level

After operation 2 or 3, the UDDRC starts bursting refreshes to compensate for any updated refresh timing parameters.