3.2.14 Force Execution Instruction Register 2⁽¹⁾

Table 3-14. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	FEX2
Offset:	0x0034

Bits 31:0 – FEX2[31:0] For 2 word operations, FEX contains the second instruction to be executed using the UFEX instruction.

FEX is only visible as a R/W register in Debug mode. In all other operating modes, it is read-only of all 0’s.