19.4.1.5.1 Host Mode Operation

Perform the following steps to set up the SPI module for Host mode operation:

  1. Disable the SPIx interrupts in the respective IECx register.
  2. Stop and reset the SPI module by clearing the ON bit.
  3. Clear the receive buffer.
  4. Clear the ENHBUF bit (SPIxCON1[0]) if using Standard Buffer mode or set the bit if using Enhanced Buffer mode.
  5. SPIx interrupts are not going to be used, skip this step. Otherwise, the following additional steps are performed:
    1. Clear the SPIx interrupt flags/events in the respective IFSx register.
    2. Write the SPIx interrupt priority and sub-priority bits in the respective IPCx register.
    3. Set the SPIx interrupt enable bits in the respective IECx register.
  6. Write the Baud Rate register, SPIxBRG.
  7. Clear the SPIROV bit (SPIxSTAT[6]).
  8. Write the desired settings to the SPIxCON1 register with MSTEN (SPIxCON1[5]) = 1.
  9. Enable SPI operation by setting the ON bit (SPIxCON1[15]).
  10. Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register.
Note: The SPI device must be turned OFF prior to changing the mode from Client to Host. (When using the Client Select mode, the SSx pin or another GPIO pin is used to control the Client’s SSx input. The pin must be controlled in software).

In Host mode, the PBCLK is divided and then used as the serial clock. The division is based on the settings in the SPIxBRG register. The serial clock is output through the SCKx pin to the client devices. Clock pulses are only generated when there is data to be transmitted; except when in Framed mode, when the clock is generated continuously. For further information, refer to SPI Host Mode Clock Frequency.

The Host Mode Client Select Enable (MSSEN) bit in the SPIx Control Register 1 (SPIxCON1[20]) can be set to automatically drive the Client Select signal (SSx) in Host mode. Clearing this bit disables the Client Select signal support in Host mode. The FRMPOL bit (SPIxCON1[21]) determines the polarity for the Client Select signal in Host mode.

Note: The MSSEN bit is not available on all devices. This bit should not be set when the SPI Framed mode is enabled (i.e., FRMEN = 1).

In devices that do not feature the MSSEN bit, the Client Select signal (in Non-Framed SPI mode) must be generated by using the SSx pin or another general purpose I/O pin under software control.

The CKP (SPIxCON1[6]) and CKE (SPIxCON1[8]) bits determine on which edge of the clock data transmission occurs.

Note: The user must turn OFF the SPI device prior to changing the CKE or CKP bits. Otherwise, the behavior of the device is not ensured.

Both data to be transmitted and data that is received are written to, or read from, the SPIxBUF register, respectively.

The following progression describes the SPI module operation in Host mode:

  1. Once the module is set up for Host mode operation and enabled, data to be transmitted is written to the SPIxBUF register. The SPITBE bit (SPIxSTAT[3]) is cleared.
  2. The contents of SPIxTXB are moved to the SPIx Shift register, SPIxTXSR (see Figure 19-9), and the SPITBE bit is set by the module.
  3. A series of 8/16/32 clock pulses shifts 8/16/32 bits of transmit data from SPIxTXSR to the SDOx pin and simultaneously shifts the data at the SDIx pin into SPIxRXSR.
  4. When the transfer is complete, the following events will occur:
    1. The SPIxRXIF interrupt flag bit is set. SPIx interrupts can be enabled by setting the SPIxRXIE interrupt enable bit. The SPIxRXIF flag is not cleared automatically by the hardware.
    2. Also, when the ongoing transmit and receive operation is completed, the contents of SPIxRXSR are moved to SPIxRXB.
    3. The SPIRBF bit (SPIxSTAT[0]) is set by the module, indicating that the receive buffer is full. Once SPIxBUF is read by the user code, the hardware clears the SPIRBF bit. In Enhanced Buffer mode, the SPIRBE bit (SPIxSTAT[5]) is set when the SPIxRXB FIFO buffer is completely empty and cleared when not empty.
  5. If the SPIRBF bit is set (the receive buffer is full) when the SPI module needs to transfer data from SPIxRXSR to SPIxRXB, the module will set the SPIROV bit (SPIxSTAT[6]) indicating an overflow condition.
  6. Data to be transmitted can be written to SPIxBUF by the user software at any time, if the SPITBE bit (SPIxSTAT[3]) is set. The write can occur while SPIxTXSR is shifting out the previously written data, allowing continuous transmission. In Enhanced Buffer mode, the SPITBF bit (SPIxSTAT[1]) is set when the SPIxTXB FIFO buffer is completely full and clear when it is not full.
Note: The SPIxTXSR register cannot be written directly by the user. All writes to the SPIxTXSR register are performed through the SPIxBUF register.
Figure 19-9. SPIx Host Mode Operation in 8-Bit Mode (MODE32 = 0, MODE16 = 0)
Note:
  1. Four SPI Clock modes are shown here to demonstrate the functionality of bits, CKP (SPIxCON1[6]) and CKE (SPIxCON1[8]). Only one of the four modes can be chosen for operation.
  2. The SDIx and input samples shown here for two different values of the SMP bit (SPIxCON1[9]) are strictly for demonstration purposes. Only one of the two configurations of the SMP bit can be chosen during operation.
  3. If there are no pending transmissions, SPIxTXB is transferred to SPIxTXSR as soon as the user writes to SPIxBUF.
  4. Operation for 8-bit mode is shown; 16-bit and 32-bit modes are similar.

Initialization Code for 16-Bit SPI Host Mode

/* The following code example will initialize the SPI1 in Host mode. */
_SPI1TXIP = 4;               // Set SPI Interrupt Priorities
SPI1BRG = 0x1;               // use FSPICLK/4 clock frequency
SPI1STATbits.SPIROV = 0;     // clear the Overflow
SPI1CON1 = 0x00000420;       // 16 bits transfer, Host mode,ckp=0,cke=0,smp=0
SPI1IMSKbits.SPITBFEN = 1;   // SPI1 transmit buffer full generates interrupt event
_SPI1TXIE = 1;               // Enable interrupts
SPI1CON1bits.ON = 1;
// from here, the device is ready to transmit and receive data. Buffer can be loaded to transmit data.