12.4.2.3.2 Setup for Using PLL with 8 MHz Internal FRC

The following process is used to set up the PLL to operate the device at 100 MHz with an 8 MHz Internal FRC and configure PLL VCO output to 250 MHz.

To execute instructions at 100 MHz, a PLL output frequency of 100 MHz will be required.
To set up the PLL and meet the requirements of the PLL, follow these steps:
1. Select the PLL prescaler to meet the PFD input frequency requirement.
  - Select a PLL prescaler value of N1 = 1
  - F_PLLI = 8 MHz
  - F_PFD = 8 MHz(1/N1) = 8 MHz(1) = 8 MHz
2. Select the feedback divider to meet the VCO output frequency requirement as well as achieve the desired F_VCO frequency.
  - Select a feedback divider value of M = 125
  - F_VCO = F_PLLI x (M/N1) = 8 MHz x (125/1) = 1 GHz
3. Select values for the first and second PLL postscalers to achieve the required F_PLLO frequency.
  - Select values for the first and second postscalers of N2 = 5 and N3 = 2
  - F_PLLO = F_VCO/(N2 x N3) = 1 GHz/10 = 100 MHz
Writing PLLxCON (can be done in one PLLxCON write):
1. Enable the PLL Input and Feedback Divider update by setting PLLSWEN bit in the PLLxCON register. Enable PLL Output Divider update by setting FOUTSWEN bit in the PLLxCON register.
2. Select clock source by setting NOSC[3:0] bits in the PLLxCON register to FRC (1).
3. Enable clock switching by setting OSWEN bit in the PLLxCON register.
PLL VCO output setup is optional for normal PLL output. PLL VCODIV output is necessary if PLL VCODIV will be chosen as a CLKGEN input. For PLL VCO output, the PLLxDIV register needs to be configured. INTDIV bits of the PLLxDIV register are configured as two.
- FVCO / INTDIV*2 = 1 GHz/ 2*2 =250 MHz

Code Example for Using PLL with 8 MHz Internal FRC illustrates code for using the PLL with an 8 MHz Internal FRC Oscillator.

Note: PLL1CON writes written out for clarity. These writes can be achieved in a single PLL1CON write.

Code Example for Using PLL with 8 MHz Internal FRC

// code example for 100MIPS PLL clock using 10MHz crystal primary oscillator
//configure backup oscillator in case of failure
//Enable PLL clock generator
PLL1CONbits.ON = 1;
PLL1CONbits.OE = 1;
PLL1CONbits.BOSC = 2;             //BFRC as backup clock source
PLL1CONbits.FSCMEN = 1;           //enable fail safe
//configure PLL values
PLL1DIVbits.PLLPRE = 1;           //Reference Clock Divider
PLL1DIVbits.POSTDIV1 = 5;         //Post Divider #1
PLL1DIVbits.POSTDIV2 = 2;         //Post Divider #2
// PLL Fout = Fin*FBDIV / (PLLPRE * POSTDIV1 * POSTDIV2)
// PLL Fout = 8M*125/(1*5*2) =100MHz
//Enable PLL Input and Feedback Divider update
PLL1CONbits.PLLSWEN = 1;
while (PLL1CONbits.PLLSWEN == 1);
//Enable PLL Output Divider update
PLL1CONbits.FOUTSWEN = 1;
while (PLL1CONbits.FOUTSWEN);
//select clock switching clock source
PLL1CONbits.NOSC = 1;             //select FRC clock source
//[1] = FRC - Internal 8 MHz RC oscillator
//[2] = BFRC - Internal Backup 8 MHz RC oscillator
//[3] = POSC - Primary crystal oscillator (4-32 MHz)
//[9] = REFI1 - user definable clock source
//[10] = REFI2 - user definable clock source
PLL1CONbits.OSWEN = 1;          //enable clock switching
while (PLL1CONbits.OSWEN);      //wait for switching(hardware clear)
while(!OSCCTRLbits.PLL1RDY)    //wait for clock to be ready
//configure PLL VCO Divider registers for PLL1 VCO Div clock source
VCO1DIVbits.INTDIV = 2;         //integer divide factor
// PLL VCO DIV = PLL VCO clock / 2* INTDIV
//Enable PLL VCO Divider update
PLL1CONbits.DIVSWEN = 1;
while (PLL1CONbits.DIVSWEN);