Reference Clock Failure

The clock monitor module can detect reference clock failure; the reference clock can fail in the following conditions:

1. If the selected reference clock is completely missing from the start, making the signaling event representing the start of the accumulation time window absent, the TRIG bit remains clear as a result. This condition can be captured by the user software’s observing the logic value of this bit once the system has booted up - no interrupt and/or other signaling event generated.
2. However, if the reference clock starts out toggling, setting the TRIG bit high, but subsequently slows down significantly or ceases to toggle completely at some point, the signaling event representing the start/stop of the accumulation time window is also affected by the same proportion. This condition effectively extends the accumulation time window causing the counter to eventually saturate before capturing in some cases. As a result, the SATD bit is set high - interrupt invoked.