Monitored Clock Failure

The monitored clock experiences a catastrophic failure and decreases its toggling rate significantly or ceases to toggle completely.

The total latency of the monitored clock frequency drift detection does not only depend on the duration of the accumulation time window on which it operates, it also depends on the latency of its clock domain crossing logic.

Detection happens on timely updates of the Data Buffer register with the captured count as the periodic accumulation time expires. At the next accumulation time expiration, if BUF[31:0] has not been updated, the monitored clock is considered to have experienced a catastrophic failure event given that the reference clock is still toggling reliably.

The module's response is similar to that of the clock frequency drifting beyond the user defined catastrophic tolerance limit described above. By asserting a clock fail event, the clock monitor module provides the system with a fast hardware response time often required to deal with a clock failure in control loop applications. The clock fail event triggers the clock fail interrupt with the conditions reflected below: