51.7.13 Software Trigger
Note: This register is write-synchronized: SYNCBUSY.SWTRIG must be checked to ensure the
SWTRIG register synchronization is complete.
| Name: | SWTRIG |
| Offset: | 0x14 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| START | FLUSH | ||||||||
| Access | W | RW | |||||||
| Reset | 0 | 0 |
Bit 1 – START Start ADC Conversion
Writing a '1' to this bit will start a conversion or sequence. The bit is cleared by hardware when the conversion has started. Writing a '1' to this bit when it is already set has no effect.
Writing a '0' to this bit has no effect.
Bit 0 – FLUSH ADC Conversion Flush
Writing a '1' to this bit will flush the ADC pipeline. A flush will restart the ADC clock on the next peripheral clock edge, and all conversions in progress will be aborted and lost. This bit will be cleared after the ADC has been flushed.
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a new conversion.
Writing a '0' to this bit has no effect.