51.7.5 Control B

Note: This register is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLB register synchronization is complete.
Name: CTRLB
Offset: 0x06
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized

Bit 15141312111098 
     WINSSWINMODE[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
    RESSEL[1:0]CORRENFREERUNLEFTADJ 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 11 – WINSS Window Single Sample

When this bit is written the window functionality is working on each conversions and not on the accumulated value. The number of convesions matching with the window comparator is available on STATUS register (STATUS.WCC). The last sample result is available on RESS register.

Bits 10:8 – WINMODE[2:0] Window Monitor Mode

These bits enable and define the window monitor mode.

ValueNameDescription
0x0 DISABLE No window mode (default)
0x1 MODE1 RESULT > WINLT
0x2 MODE2 RESULT < WINUT
0x3 MODE3 WINLT < RESULT < WINUT
0x4 MODE4 !(WINLT < RESULT < WINUT)
0x5 - 0x7 Reserved

Bits 4:3 – RESSEL[1:0] Conversion Result Resolution

These bits define whether the ADC completes the conversion 12-, 10- or 8-bit result resolution.
ValueNameDescription
0x0 12BIT 12-bit result
0x1 16BIT For averaging mode output
0x2 10BIT 10-bit result
0x3 8BIT 8-bit result

Bit 2 – CORREN Digital Correction Logic Enable

The ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCORR and OFFSETCORR registers. Conversion time will be increased by 13 cycles according to the value in the Offset Correction Value bit group in the Offset Correction register.
ValueDescription
0 Disable the digital result correction
1 Enable the digital result correction

Bit 1 – FREERUN Free Running Mode

ValueDescription
0 The ADC run in single conversion mode
1 The ADC is in free running mode and a new conversion will be initiated when a previous conversion completes

Bit 0 – LEFTADJ Left-Adjusted Result

The high byte of the 12-bit result will be present in the upper part of the result register. Writing this bit to zero (default) will right-adjust the value in the RESULT register.
ValueDescription
0 The ADC conversion result is right-adjusted in the RESULT register
1 The ADC conversion result is left-adjusted in the RESULT register