51.7.6 Reference Control
Note: This register is write-synchronized: SYNCBUSY.REFCTRL must be checked to ensure the
REFCTRL register synchronization is complete.
| Name: | REFCTRL |
| Offset: | 0x08 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| REFCOMP | REFSEL[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 7 – REFCOMP Reference Buffer Offset Compensation Enable
The gain error can be reduced by enabling the reference buffer offset compensation. This will increase the start-up time of the reference.
Note: If the reference buffer offset
compensation is enabled (REFCOMP = 1) and the ADC reference selection is not using
VDDANA (REFSEL ! = INTVCC1), the first 5 conversions of the ADC must be discarded
after the ADC is enabled.
| Value | Description |
|---|---|
| 0 | Reference buffer offset compensation is disabled. |
| 1 | Reference buffer offset compensation is enabled. |
Bits 3:0 – REFSEL[3:0] Reference Selection
These bits select the reference for the ADC.
Note: If the internal bandgap voltage
reference is selected (REFCTRL.REFSEL = 0x0), the On Demand operation mode
(CTRLA.ONDEMAND = 0) is not supported and a delay of minimum 40 µs must be respected
between the enable of the ADC (CTRLA.ENABLE) and the start of the first conversion.
In case an ADC conversion is triggered by an input event, the delay must be
introduced between the enable of the ADC and the enable of the ADC EVSYS channel.
| Value | Name | Description |
|---|---|---|
| 0x0 | INTREF | internal bandgap reference, refer to the VREF.SEL bit-field in SUPC-Supply Controller for more details |
| x01 | Reserved | |
| 0x2 | INTVCC0 | 1/2 AVDD (only for AVDD > 2.0V) |
| 0x3 | INTVCC1 | AVDD |
| 0x4 | AREFA | External reference |
| 0x5 | AREFB | External reference |
| 0x6 | AREFC | External reference (ADC1 only) |
| other | - | Reserved |