51.7.8 Sampling Time Control
Note: This register is write-synchronized: SYNCBUSY.SAMPCTRL must be checked to ensure the
SAMPCTRL register synchronization is complete.
| Name: | SAMPCTRL |
| Offset: | 0x0B |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OFFCOMP | SAMPLEN[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – OFFCOMP Comparator Offset Compensation Enable
Setting this bit enables the offset compensation for each sampling period to ensure low offset and immunity to temperature or voltage drift. ADC sampling time is fixed to 4 ADC Clock cycles when OFFCOMP = 1.
Bits 5:0 – SAMPLEN[5:0] Sampling Time Length
These bits control the ADC sample time (TSAMP) in number of ADC Clock Period (CLK_ADC aka TAD), depending on the prescaler value, thus controlling the ADC input impedance. Sampling time is set according to the equation:
SAMPLEN is only available when OFFCOMP = 0.
Note: Refer to ADC Electrical Characteristics for TSAMP computation.