51.7.1 Control A


Bit	15	14	13	12	11	10	9	8
	R2R					PRESCALER[2:0]
Access	R/W					R/W	R/W	R/W
Reset	0					0	0	0


Bit	7	6	5	4	3	2	1	0
	ONDEMAND	RUNSTDBY	SLAVEEN	DUALSEL[1:0]			ENABLE	SWRST
Access	R/W	R/W	R/W	R/W	R/W		R/W	R/W
Reset	0	0	0	0	0		0	0

Bit 15 – R2R Rail to Rail Operation Enable

Value	Description
0	Rail-to-Rail operation disable
1	Rail-to-Rail operation enable. The R2R bit must be set to ‘1’ only in differential mode.

Bits 10:8 – PRESCALER[2:0] Prescaler Configuration

This field defines the ADC clock relative to the peripheral clock as provided in the table below. This field is not synchronized. For the Client ADC, these bits have no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN = 1).

Note: ADC DMA Sequencing operations are limited to DIV2, DIV4 and DIV8 prescalers configuration.

Value	Name	Description
0x0	DIV2	Peripheral clock divided by 2
0x1	DIV4	Peripheral clock divided by 4
0x2	DIV8	Peripheral clock divided by 8
0x3	DIV16	Peripheral clock divided by 16
0x4	DIV32	Peripheral clock divided by 32
0x5	DIV64	Peripheral clock divided by 64
0x6	DIV128	Peripheral clock divided by 128
0x7	DIV256	Peripheral clock divided by 256

Bit 7 – ONDEMAND On Demand Control

The On Demand operation mode allows the ADC to be enabled or disabled, depending on other peripheral requests.

In On Demand operation mode, that is, if the ONDEMAND bit has been previously set, the ADC will only be running when requested by a peripheral. If there is no peripheral requesting the ADC will be in a disable state.

If On Demand is disabled the ADC will always be running when enabled.

In Standby Sleep mode, the On Demand operation is still active if the CTRLA.RUNSTDBY bit is '1'. If CTRLA.RUNSTDBY is '0', the ADC is disabled.

This bit is not synchronized.

Note: For the Client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN = 1). ONDEMAND bit from Host ADC instance will control the On Demand operation mode.

Value	Description
0	The ADC is always on , if enabled.
1	The ADC is enabled, when a peripheral is requesting the ADC conversion. The ADC is disabled if no peripheral is requesting it.

Bit 6 – RUNSTDBY Run in Standby

This bit controls how the ADC behaves during Standby Sleep mode.

This bit is not synchronized.

Note: For the Client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN = 1). The RUNSTDBY bit from Host ADC instance will control the Client ADC operation in Standby Sleep mode.

Value	Description
0	The ADC is halted during Standby Sleep mode.
1	The ADC is not stopped in Standby Sleep mode. If CTRLA.ONDEMAND = 1, the ADC will be running when a peripheral is requesting it. If CTRLA.ONDEMAND = 0, the ADC will always be running in Standby Sleep mode.

Bit 5 – SLAVEEN Client Enable

This bit enables the Host or Client operation, and it is available only in the Client ADC instance.

This bit is not synchronized and can be set only for the Client ADC. For the Host ADC, this bit is always read zero.

Value	Description
0	The Host/Client operation is disabled
1	The ADC1 is enabled as a Client of ADC0

Bits 4:3 – DUALSEL[1:0] Dual Mode Trigger Selection

These bits define the trigger mode, as shown in Table below. These bits are available in the Host ADC and have no effect if the Host/Client operation is disabled (ADC1.CTRLA.SLAVEEN = 0).

Value	Name	Description
0x0	BOTH	Start event or software trigger will start a conversion on both ADCs
0x1	INTERLEAVE	START event or software trigger will alternatingly start a conversion on ADC0 and ADC1. Note: The interleaved sampling is only usable in single conversion mode (ADC.CTRLB.FREERUN = 0).
0x2 - 0x3		Reserved

Bit 1 – ENABLE Enable

Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the ENABLE bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. The SYNCBUSY.ENABLE register will be cleared when the operation is complete.

For the Client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN = 1).

Value	Description
0	The ADC is disabled.
1	The ADC is enabled.

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be disabled.

Writing a '1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.

Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

Note:

When the CTRLA.SWRST is written, the user must poll the SYNCBUSY.SWRST bit to know when the reset operation is complete.
During a SWRST, access to registers/bits without the SWRST are disallowed until the SYNCBUSY.SWRST is cleared by hardware.