51.7.18 Synchronization Busy

Name: SYNCBUSY
Offset: 0x30
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     SWTRIGOFFSETCORRGAINCORRWINUT 
Access RRRR 
Reset 0000 
Bit 76543210 
 WINLTSAMPCTRLAVGCTRLREFCTRLCTRLBINPUTCTRLENABLESWRST 
Access RRRRRRRR 
Reset 00000000 

Bit 11 – SWTRIG Software Trigger Synchronization Busy

This bit is cleared when the synchronization of SWTRIG register between the clock domains is complete.

This bit is set when the synchronization of SWTRIG register between clock domains is started.

Note:
  1. For the Client ADC, this bit is always read zero when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1).
  2. SYNCBUSY.SWTRIG is set to 1 when waking up from Standby Sleep mode and must be ignored.

Bit 10 – OFFSETCORR Offset Correction Synchronization Busy

This bit is cleared when the synchronization of OFFSETCORR register between the clock domains is complete.

This bit is set when the synchronization of OFFSETCORR register between clock domains is started.

Bit 9 – GAINCORR Gain Correction Synchronization Busy

This bit is cleared when the synchronization of GAINCORR register between the clock domains is complete.

This bit is set when the synchronization of GAINCORR register between clock domains is started.

Bit 8 – WINUT Window Monitor Upper Threshold Synchronization Busy

This bit is cleared when the synchronization of WINUT register between the clock domains is complete.

This bit is set when the synchronization of WINUT register between clock domains is started.

Bit 7 – WINLT Window Monitor Lower Threshold Synchronization Busy

This bit is cleared when the synchronization of WINLT register between the clock domains is complete.

This bit is set when the synchronization of WINLT register between clock domains is started.

Bit 6 – SAMPCTRL Sampling Time Control Synchronization Busy

This bit is cleared when the synchronization of SAMPCTRL register between the clock domains is complete.

This bit is set when the synchronization of SAMPCTRL register between clock domains is started.

Bit 5 – AVGCTRL Average Control Synchronization Busy

This bit is cleared when the synchronization of AVGCTRL register between the clock domains is complete.

This bit is set when the synchronization of AVGCTRL register between clock domains is started.

Bit 4 – REFCTRL Reference Control Synchronization Busy

This bit is cleared when the synchronization of REFCTRL register between the clock domains is complete.

This bit is set when the synchronization of REFCTRL register between clock domains is started.

Bit 3 – CTRLB Control B Synchronization Busy

This bit is cleared when the synchronization of CTRLB register between the clock domains is complete.

This bit is set when the synchronization of CTRLB register between clock domains is started.

Bit 2 – INPUTCTRL Input Control Synchronization Busy

This bit is cleared when the synchronization of INPUTCTRL register between the clock domains is complete.

This bit is set when the synchronization of INPUTCTRL register between clock domains is started.

Bit 1 – ENABLE ENABLE Synchronization Busy

This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.

This bit is set when the synchronization of ENABLE register between clock domains is started.

Note: For the Client ADC, this bit is always read zero when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1).

Bit 0 – SWRST SWRST Synchronization Busy

This bit is cleared when the synchronization of SWRST register between the clock domains is complete.

This bit is set when the synchronization of SWRST register between clock domains is started