41.8.13 GMAC Interrupt Mask Register

This register is a read-only register indicating which interrupts are masked. All bits are set at Reset and can be reset individually by writing to the Interrupt Enable Register (IER), or set individually by writing to the Interrupt Disable Register (IDR).

For test purposes there is a write-only function to this register that allows the bits in the Interrupt Status Register to be set or cleared, regardless of the state of the mask register. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written.

The following values are valid for all listed bit names of this register when read:

0: The corresponding interrupt is enabled.

1: The corresponding interrupt is not enabled.

Name: IMR
Offset: 0x030
Reset: 0x03FFFFFF
Property: -

Bit 3130292827262524 
   TSUCMPWOLRXLPISBCSRIPDRSFTPDRQFT 
Access WRRRRR 
Reset 111011 
Bit 2322212019181716 
 PDRSFRPDRQFRSFTDRQFTSFRDRQFR   
Access RRRRRR 
Reset 111111 
Bit 15141312111098 
 EXINTPFTRPTZPFNZHRESPROVR   
Access RRRRRR 
Reset 111111 
Bit 76543210 
 TCOMPTFCRLEXTURTXUBRRXUBRRCOMPMFS 
Access RRRRRRRR 
Reset 11111111 

Bit 29 – TSUCMP TSU Timer Comparison

Indicates TSU times count and comparison value are equal.

Bit 28 – WOL Wake On LAN

WOL interrupt. Indicates a WOL message has been received.

Bit 27 – RXLPISBC RXLPI Indication

Bit 26 – SRI TSU Seconds Register Increment

Indicates the register has incremented.

Cleared on read.

Bit 25 – PDRSFT PDelay Response Frame Transmitted

Bit 24 – PDRQFT PDelay Request Frame Transmitted

Bit 23 – PDRSFR PDelay Response Frame Received

Bit 22 – PDRQFR PDelay Request Frame Received

Bit 21 – SFT PTP Sync Frame Transmitted

Bit 20 – DRQFT PTP Delay Request Frame Transmitted

Bit 19 – SFR PTP Sync Frame Received

Bit 18 – DRQFR PTP Delay Request Frame Received

Bit 15 – EXINT External Interrupt

Bit 14 – PFTR Pause Frame Transmitted

Bit 13 – PTZ Pause Time Zero

Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received

Bit 11 – HRESP HRESP Not OK

Bit 10 – ROVR Receive Overrun

Bit 7 – TCOMP Transmit Complete

Bit 6 – TFC Transmit Frame Corruption Due to AHB Error

Bit 5 – RLEX Retry Limit Exceeded

Bit 4 – TUR Transmit Underrun

Bit 3 – TXUBR TX Used Bit Read

Bit 2 – RXUBR RX Used Bit Read

Bit 1 – RCOMP Receive Complete

Bit 0 – MFS Management Frame Sent