4.9.3.3.1.4 EECR – EEPROM Control Register

Name: EECR
Offset: 0x01F
Reset: 0x00

Bit 76543210 
 NVMBSYEEPAGEEEPM[1:0]EERIEEEMWEEEWEEERE 
Access RR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – NVMBSY Non-volatile Memory Busy

The NVMBSY bit is a status bit that indicates that the NVM memory (FLASH, EEPROM, lock-bits) is busy programming. Once a program operation is started, the bit is set and remains set until the program operation is completed.

Bit 6 – EEPAGE EEPROM Page Access (Multiple Bytes Access Mode)

Writing EEPAGE to ‘1’ enables multiple bytes access mode. This means that several bytes can be programmed simultaneously into the EEPROM. After the EEPAGE bit is written to ‘1’, the EEPAGE bit remains set until an EEPROM program operation is completed. Alternatively, the bit is cleared when the temporary EEPROM buffer is flushed in software (see EEPM bits description). Any write to EEPAGE while EEWE is ‘1’ is ignored. For more details on how to load data into the temporary EEPROM page and the usage of the EEPAGE bit, see Programming Multiple Bytes in One Atomic Operation in the EEPROM Data Memory from Related Links.

Bits 5:4 – EEPM[1:0] EEPROM Programming Mode Bits

The EEPROM programming mode selects a programming action that is executed when EEWE is set. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations into two different operations. The programming times for the different modes show in the following table. While EEWE is set, any write to EEPM is ignored. During reset, the EEPM bits are reset to 0b00 unless the EEPROM is busy programming.
Table 4-51. EEPROM Mode Bits
EEPM1EEPM0Programming TimeOperation
00TEE_ER_WR(1)Erase and write in one operation (atomic operation)
01TEE_ER(1)Erase only
10TEE_WR(1)Write only
11—Flush temporary EEPROM page buffer
Note: For more details on the timing values, see Timing Characteristics from Related Links.

Bit 3 – EERIE EEPROM Ready Interrupt Enable

Writing EERIE to ‘1’ enables the EEPROM ready interrupt if the I bit in SREG is set. Writing EERIE to ‘0’ disables the interrupt. The EEPROM ready interrupt generates a constant interrupt when EEWE is cleared.

Bit 2 – EEMWE EEPROM Host Write Enable

The EEMWE bit determines whether setting EEWE to ‘1’ causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles writes data to the EEPROM at the selected address. If EEMWE is ‘0’, setting EEWE has no effect. After EEMWE is written to ‘1’ by software, hardware clears the bit to ‘0’ after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

Bit 1 – EEWE EEPROM Write Enable

The EEPROM Write Enable signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to ‘1’ to write the value into the EEPROM. The EEMWE bit must be written to ‘1’ before a logical ‘1’ is written to EEWE, otherwise, no EEPROM write takes place. The following procedure must be followed when writing the EEPROM (the order of steps 3 and 4 is not important):
  1. Wait until EEWE becomes ‘0’.
  2. Wait until SELFPRGM in SPMCSR becomes ‘0’.
  3. Write new EEPROM address to EEAR (optional).
  4. Write new EEPROM data to EEDR (optional).
  5. Write a logical ‘1’ to the EEMWE bit while writing a ‘0’ to EEWE in EECR.
  6. Within four clock cycles after setting EEMWE, write a logical ‘1’ to EEWE.
The EEPROM cannot be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a bootloader allowing the CPU to program the Flash. If the Flash is never updated by the CPU, step 2 can be omitted. See Memory Access via SPM/LPM from Related Links.
CAUTION: An interrupt between step 5 and step 6 makes the write cycle fail because the EEPROM host write enable times out. If an interrupt routine accessing the EEPROM interrupts another EEPROM access, the EEAR or EEDR register is modified, causing the interrupted EEPROM access to fail. It is recommended that the global interrupt flag be cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a ‘0’ before writing the next byte. After EEWE is set, the CPU is stopped for two cycles before the next instruction is executed.

Bit 0 – EERE EEPROM Read Enable

The EEPROM Read Enable signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic ‘1’ to trigger the EEPROM read. The EEPROM read access takes one instruction and the requested data is available immediately. When the EEPROM is read, the CPU is stopped for four cycles before the next instruction is executed. The user must poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM nor change the EEAR register.