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UHF ASK/FSK Receiver User's Guide

ATA8210 ATA8215

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4 Hardware
4.9 AVR Controller
4.9.3 Memories
4.9.3.3 EEPROM Data Memory
4.9.3.3.1 EEPROM Register Description

Introduction
Features
1 Quick References
2 General Product Description
3 System Functional Description
4 Hardware
- 4.1 Overview
- 4.2 Crystal Oscillator
- 4.3 Fractional-N PLL
- 4.4 Receive Path
- 4.5 Data and Support FIFOs
- 4.6 SPDT RF Switch
- 4.7 RF Front-End Register Description
- 4.8 Sequencer State Machine
- 4.9 AVR Controller
  - 4.9.1 AVR Controller Sub-System Overview
  - 4.9.2 CPU Core
  - 4.9.3 Memories
    - 4.9.3.1 Program Memory
    - 4.9.3.2 SRAM Data Memory
    - 4.9.3.3 EEPROM Data Memory
      - 4.9.3.3.1 EEPROM Register Description
        4.9.3.3.1.1 EEARH, EEARL – EEPROM Address Register High and Low Byte
        EEARH, EEARL – EEPROM Address Register High and Low Byte
        4.9.3.3.1.2 EEDR – EEPROM Data Register
        EEDR – EEPROM Data Register
        4.9.3.3.1.3 EEPR – EEPROM Protect Register
        EEPR – EEPROM Protect Register
        4.9.3.3.1.4 EECR – EEPROM Control Register
        EECR – EEPROM Control Register
        4.9.3.3.1.5 EECR2 – EEPROM Control Register 2
        EECR2 – EEPROM Control Register 2
    - 4.9.3.4 I/O Memory
    - 4.9.3.5 General Purpose I/O Register
  - 4.9.4 System Clock and Clock Options
  - 4.9.5 Sleep Modes and Active Power Reduction
  - 4.9.6 I/O Ports
  - 4.9.7 Timer Module
  - 4.9.8 SPI – Serial Peripheral Interface
  - 4.9.9 CRC
  - 4.9.10 debugWIRE – On-Chip Debug System
  - 4.9.11 Memory Access via SPM/LPM
  - 4.9.12 Memory Programming
  - 4.9.13 Specific Interrupts Handling
  - 4.9.14 External Interrupts
- 4.10 Power Management
5 Application
6 Timing Characteristics
7 Appendix
8 Document Revision History
Microchip Information

4.9.3.3.1 EEPROM Register Description

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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