11 CAN Controller

SmartFusion 2 SoC FPGAs contain an integrated Control Area Network (CAN) peripheral. The CAN controller is an advanced peripheral bus (APB_1) slave on the MSS AHB bus matrix. For a detailed description, see 6 AHB Bus Matrix. A master such as the Cortex-M3 processor or a master in the FPGA fabric configures the CAN controller through the APB slave.

The CAN controller in the SmartFusion 2 device supports the concept of mailboxes. It is compliant to the international CAN standard defined in ISO 11898-1. It contains 32 receive buffers. Each buffer has its own message filter and 32 transmit buffers with prioritized arbitration scheme. For optimal support of Higher-Layer Protocols (HLP) such as DeviceNet, the message filter also covers the first two data bytes of the message payload. The following figure shows the block diagram of the CAN controller. Transmit and receive message buffers are Single Error Corrected, Double Error Detected (SECDED) through the Error Detection and Correction (EDAC) controller. The functional behavior of the CAN instance must be defined at the application level using the SmartFusion 2 MSS CAN firmware driver provided by Microchip. For more information, see CAN Firmware Driver User Guide.