26 Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Table 26-1. Revision History
Revision	Date	Description
A	02/2023	Remapping eNVM data from eNVM_1 memory block to Cortex®-M3 Code space is not permitted for SmartFusion® 2 M2S090/150 and IGLOO® 2 M2GL090/150 devices. For information about eNVM remapping and limitation, see the note under Figure 4-28. Timing models for Fabric to MSS interrupts have been updated with additional time delay. This changes the timing arcs of nets and interface between Fabric to MSS interrupts. For more information about the updated timing arcs, see PCN 17005A. Updated 1.5.2.3 Embedded Trace Macrocell to include information about timing arcs update from Fabric to Embedded Trace Macrocell. Updated 10.5.1 SGMII Interface Configuration to include information about timing arcs update from SerDes to Fabric. Updated 22.3.1 Configuring the FIIC Using the Libero SoC to include information about timing arcs update from Fabric to MSS interrupts. The document was converted to Microchip template. The document number was changed to DS50003495 from UG0331.
16.0	—	Information about 3.2.3.3.1 Accessing I and D Buses Concurrently was updated. Information about 19.2.3.3.1 WDOGTIMEOUTINT was updated. Information about 19.3 How to Use the Watchdog Timer was updated. Information about 20.2.6.3.2 PO_RESET_RCOSC_N was updated.
15.0	—	1.7.1 Configuration Through Libero Software and Firmware updated. TESMAC Firmware Drivers information updated in Table 10-8, Table 10-9, Table 10-10, Table 10-11. Updated register information in Table 12-5, Table 21-17, Table 21-44, Table 21-73, Table 21-74, Table 21-75, Table 21-76, Table 21-77, and Table 21-78. Updated 9.2.2.1 ULPI (UTMI+ Low Pin Interface) I/O Interface.
14.0	—	The power-up to functional time sequence information was updated to include the POWER_ON_RESET_N signal. For more information, see 20.1.2 Power-Up to Functional Time Sequence. The test cases listed in Table 20-1 were updated for consistency with IGLOO2 and SmartFusion2 Datasheet. The VDD power-up to functional time flow diagram (Figure 20-8) was updated to include the POWER_ON_RESET_N signal. For more information, see 20.2.2 VDD Power-Up to Functional Time. The test cases listed in Table 20-2 were updated for consistency with IGLOO2 and SmartFusion2 Datasheet. The DEVRST_N power-up to functional time flow diagram (Figure 20-10) was updated to include the POWER_ON_RESET_N signal. For more information, see 20.2.3 DEVRST_N Power-Up to Functional Time.
13.0	—	Updated 2.5.5 Power Management. Updated Table 2-66. Added 21.5.1 System Registers Behavior for M2S005/010 Devices. Updated Table 21-89. Updated 21.5.19 Software Reset Control Register. Updated Figure 4-18, Figure 4-19, Figure 4-20, Figure 4-21, and Figure 4-22. Updated Table 4-21.
12.0	—	Updated Table 21-2. Updated bit name from MSS_IOMUXSEL4UPPER[N] to MSS_IOMUXSEL4[N][2:0] in the Table 21-114. Added 21.3 Register Lock Bits Configuration. Updated Table 23-1. Updated 20.1.1 Power-On Reset Generation Sequence. Updated Bit number [18:1] description in Table 21-10. Updated Register name CLRHINT[2:0] row in Table 4-20. Updated £ to ≤ in 1 Cortex-M3 Processor Overview and Debug Features. Added Figure 4-21 (M2S060 device). Added clocking information to 10.2.1.5 SGMII Module. Added information regarding full behavioral simulation model in the applicable chapters. Removed note from 11.3.1 Peripheral Signals Assignment Table, and removed “System Clock Frequency” section. Added 20.2 Power-Up to Functional Time Data. Added 25 Error Detection and Correction Controllers. Updated Figure 10-2, Figure 10-4, Figure 10-9, and Figure 10-10. Added a note for 1.2 Functional Description in 1 Cortex-M3 Processor Overview and Debug Features. Updated Table 19-8 and Table 19-9. Updated Bit number 2 description in Table 21-44.
11.0	—	Updated Table 10-48 and Table 10-49. Updated 6.1.4.7 Locked Transactions.
10.0	—	Updated 20.1.2 Power-Up to Functional Time Sequence. Updated Table 12-18. Updated 4.2 Functional Description chapter in 4 Embedded NVM (eNVM) Controllers chapter. Updated Table 21-92 and Table 4-18. Added Figure 4-18, Figure 4-19, Figure 4-20, and Figure 4-22, and added 4.3.2 eNVM Pages for Special Purpose Storage. Updated 13.3.2 SPI Use Models. Updated Table 4-12, Table 4-20, and Table 21-8.
9.0	—	Updated 20 Reset Controller. Updated Figure 20-22. Added a note to 20.2.5 System Reset. Updated FIC 23.5 Implementation Considerations.
8.0	—	Removed M2S100 devices list from 4.1 Features, Table 4-1, Table 4-2, and Table 4-22. Updated Table 4-12 for NV_FREQRNG and replaced FREQRNG with NV_FREQRNG throughout the document. Updated 4.2.5.2 Page Program. Updated 21 System Register Block. Added a reference to SmartFusion 2 SoC FPGA High Speed DDR Interfaces User Guide in the 7.3.2 HPDMA Use Models.
7.0	—	Updated 3.2.3.3 Cache Engine.
6.0	—	Added a note to 1.7.1.5 Trace Port Interface Unit (TPIU) Configuration. Updated Table 1-3 and Table 1-4. Updated Table 1-4. Updated 2.5.2.2 Memory System Ordering of Memory Accesses. Updated 2.5.5 Power Management. Changed S bus to SBUS in 3 Cache Controller. Added a note to 3.2.4 Cache Locked Mode. Added notes in 4.4 How to Use eNVM. Updated 4.2.5.4 Set Lock Bit and User Unlock Commands. Added a note to 4.2.5.2 Page Program. Added 4.2.5.6 eNVM Program and Verify Operations Timing Diagrams. Updated the HPDMA 7.2.3 Details of Operation. Updated 8.2.4.2 Posted APB Writes. Added a note to 9.2.1.6 PHY Interfaces and to 9.2.2.1 ULPI (UTMI+ Low Pin Interface) I/O Interface. Updated Table 10-4. Updated Table 10-2. Added 10.9 CoreMACFilter Overview. Updated Table 13-9 for TXRXDFCOUNT value. Updated 15.2 MSS GPIO Functional Description. Added a note to 15.4.5 GPIO Input Source Select Control Register. Added a note to 20.1.1 Power-On Reset Generation Sequence. Updated Table 21-114 for bit numbers. Updated Table 22-7. Updated the introductory content of 23 Fabric Interface Controller, and added a note to Figure 23-11. Updated 4 Embedded NVM (eNVM) Controllers, 5 Embedded SRAM (eSRAM) Controllers, 6 AHB Bus Matrix, 7 High Performance DMA Controller, 8 Peripheral DMA, 13 Serial Peripheral Interface Controller, 16 Communication Block, 21 System Register Block, 22 Fabric Interface Interrupt Controller, and 23 Fabric Interface Controller chapters for FTC comments.
5.0	—	Updated the document. Updated Figure 20-15 and Figure 20-16. Updated Figure 23-31.
4.0	—	Corrected all instances of baud rate. References to 1.0 v were removed. Updated 3.1 Features of 3 Cache Controller. Added a reference to the Remapping eNVM, eSRAM, and DDR/SDR SDRAM Memories application note. Updated Figure 3-2. Updated eNVM 4.2.4 Theory of Operation. Updated Figure 6-12, Figure 6-13, and Figure 6-17, Table 6-4, and Table 6-8. Updated the direction for ULPI_XCLK in Table 9-1. Updated Table 10-25. Updated Figure 15-1. Updated Table 17-11. Updated 20.2.4 Power-On Reset. Updated Table 21-2, Table 21-44, and Table 21-66. Updated details for CC_EDAC_EN in Table 21-20. Updated Table 21-86. Updated Table 21-114. Updated details for CC_EDAC_EN in Table 5-21.
3.0	—	The following changes were made in revision 3.0 of this document. Updated “Purpose” section. Updated Table 10-2. Updated links in 11 CAN Controller. Restructured 23 Fabric Interface Controller as per inputs.
2.0	—	The following changes were made in revision 2.0 of this document. Modified the title of the user guide. Restructured 1 Cortex-M3 Processor Overview and Debug Features. Restructured 3 Cache Controller. Restructured 4 Embedded NVM (eNVM) Controllers and updated Table 4-4. Restructured 5 Embedded SRAM (eSRAM) Controllers. Restructured 6 AHB Bus Matrix. Restructured 7 High Performance DMA Controller. Restructured 8 Peripheral DMA. Restructured 9 Universal Serial Bus On-The-Go Controller. Restructured 10 Ethernet MAC. Restructured 11 CAN Controller. Restructured 12 MMUART Peripherals. Restructured 13 Serial Peripheral Interface Controller. Restructured 14 Inter-Integrated Circuit Peripherals. Restructured 15 MSS GPIO. Restructured 16 Communication Block. Restructured 17 RTC System. Restructured 18 System Timer. Restructured 19 Watchdog Timer. Restructured 20 Reset Controller and updated 20.1.2 Power-Up to Functional Time Sequence. Updated Figure 20-20. Restructured 21 System Register Block. Updated the “Flash Write ProtectSYSREG Block Register Write Protection” section. Updated Table 21-9, Table 21-90, Table 21-115, and Table 21-116. Restructured 22 Fabric Interface Interrupt Controller. Restructured 23 Fabric Interface Controller. Restructured 24 APB Configuration Interface. Updated 6.1.4.4 DDR Remap. Updated Table 23-3.
1.0	—	Revision 1.0 was the first publication of this document. Updated 3 Cache Controller. Table 3-2, Figure 3-2, and Table 3-4. Added Figure 16-1. Added Figure 23-3 through Figure 23-11.