2 Cortex-M3 Processor (Reference Material)

The Cortex-M3 processor is a high performance 32-bit processor designed for the microcontroller market. It offers the following significant benefits to developers:

  • Outstanding processing performance combined with fast interrupt handling
  • Enhanced system debug with extensive breakpoint and trace capabilities
  • Efficient processor core, system, and memories
  • Ultra-low power consumption with integrated Sleep modes
  • Robust platform security, with optional integrated memory protection unit (MPU)
Figure 2-1. Cortex-M3 Processor Implementation

The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division.

To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex-M3 processor instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.

The Cortex-M3 processor closely integrates a configurable nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. NVIC in SmartFusion 2 SoC FPGA MSS is set to have 83 interrupts (including non-maskable interrupt).The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency.

This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in assembly code, removing any code overhead from the ISRs. A Tail-chain optimization also significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down while still retaining program state.