25 Error Detection and Correction Controllers

In SEU susceptible environments, which are increasingly more common at ground-level due to shrinking geometries, storage elements such as RAMs and FIFOs in the microcontroller subsystem (MSS) are susceptible to transient errors caused by heavy ions. Errors can be detected and corrected by employing error detection and correction (EDAC). The EDAC controllers implemented in SmartFusion 2 devices support single error correction and double error detection (SECDED).

SmartFusion 2 SOC memories such as eSRAM, eNVM, USB internal memory, internal FIFOs of the Ethernet MAC, and the internal RAM of the controller area network (CAN) controller are protected by EDAC. Fabric SRAM blocks are not protected by EDAC.