7 High Performance DMA Controller

The High Performance DMA (HPDMA) controller provides fast data transfer between the MSS DDR bridge and MSS memories. The MSS memories are eSRAM0, eSRAM1, eNVM0, and eNVM1. The DDR bridge connects to External DDR memory.

The following figure shows HPDMA interfacing with AHB Bus Matrix and MSS DDR bridge. AHB bus masters such as the Cortex-M3 processor can offload the high speed memory transfers to HPDMA, making the master available for performing other tasks. All transfers by the HPDMA are full word transfers. The HPDMA controller has two AHB masters, MSS DDR Bridge and AHB bus matrix master (MM0-MM9), which functions concurrently to enable high performance data transfers. The configuration of HPDMA is done through the APB interface.

One of the main applications for which the HPDMA can be used is paging access by the processor. The main data is stored in a large DDR space and relevant chunks of this data would be transferred as needed via the HPDMA to the eSRAM, where it can be processed faster.