6 AHB Bus Matrix

The AHB bus matrix is a multi-layer AHB matrix. It is not a full crossbar switch, but a customized subset of a full switch. It works purely as an AHB-Lite matrix. The SmartFusion 2 SoC FPGA AHB bus matrix has 10 masters and seven direct slaves as depicted in the following figure. One master is permitted to access a slave at the same time another master is accessing a different slave. If more than one master is attempting to access the same slave simultaneously, arbitration for that slave is performed. Arbitration is not purely round robin or weighted round robin (WRR), but it is a combination of priority, round robin for processor-related masters, and WRR for non-processor masters.

The preceding figure depicts the connectivity of masters and slaves in the AHB bus matrix. MM0 and MS0 refers to a mirrored master and a mirrored slave. A mirrored master port in the matrix connects directly to an AHB master; it has the same set of signals, but the direction of the signals is described relative to the other end of the connection.

A mirrored slave port in the matrix connects directly to an AHB slave. Only a subset of the full set of theoretical paths is implemented within the AHB bus matrix. The AHB bus matrix performs the address decoding of all slaves except for slaves that connect to the AHB-to-AHB bridge.