20 Reset Controller

The Reset Controller manages the asynchronous reset requests coming from various sources and generates a synchronous reset for the entire MSS or individual resets to the MSS sub-blocks and user logic in the FPGA fabric.

The Reset Controller drives resets to various modules of the SmartFusion 2 devices, such as the 
Cortex-M3 processor, MDDR subsystem, Watchdog Timer, FPGA fabric, MSS GPIO, clock controller, SYSREG, and peripherals. The following figure shows the Reset Controller with various reset inputs/outputs from/to various MSS blocks.

Microchip recommends to use the CoreResetP IP for initializing the user design in SmartFusion 2 devices. The CoreResetP handles the sequencing of reset signals in SmartFusion 2 devices. It is available in the Libero System-on-Chip (SoC) IP catalog. The System Builder is a powerful design tool within the Libero SoC Design Environment that helps you capture your system-level requirements and produce a design implementing those requirements. A very important function of the System Builder is the automatic creation of the “initialization” sub-system (all required cores are instantiated, and connections are made automatically).