32.6.1 Digital Filter/Average

The digital filter/average module consists of an accumulator with data feedback options, and a control logic to determine when threshold tests need to be applied. The accumulator is a 16-bit wide register that can be accessed through the ADACCH:ADACCL register pair.

Upon each trigger event (the GO bit set or external event trigger), the ADC conversion result is added to the accumulator. If the accumulated result exceeds 2(accumulator_width)-1, the OV Accumulator Overflow bit is set.
The number of samples to be accumulated is determined by the ADRPT (A/D Repeat Setting) register. Each time a sample is added to the accumulator, the ADCNT register is incremented. Once ADRPT samples are accumulated (ADCNT = ADRPT), an accumulator clear command can be issued by the software by setting the ACLR bit. Setting the ACLR bit will also clear the OV bit, as well as the ADCNT register. The ACLR bit is cleared by the hardware when the accumulator clearing action is complete.
Important: When ADC is operating from FRC, five FRC clock cycles are required to execute the ADACC clearing operation.

The CRS bits control the data shift on the accumulator result, which effectively divides the value in accumulator (ADACCU:ADACCH:ADACCL) register pair. For the Accumulate mode of the digital filter, the shift provides a simple scaling operation. For the Average/Burst Average mode, the Shift bits are used to determine the number of logical right shifts to be performed on the accumulated result. For the Low-Pass Filter mode, the shift is an integral part of the filter, and determines the cut-off frequency of the filter. The table below shows the -3 dB cut-off frequency in ωT (radians) and the highest signal attenuation obtained by this filter at nyquist frequency (ωT = π).

Table 32-3. Low-Pass Filter -3 dB Cut-off Frequency
CRS ωT (radians) @ -3 dB Frequency dB @ Fnyquist = 1/(2T)
1 0.72 -9.5
2 0.284 -16.9
3 0.134 -23.5
4 0.065 -29.8
5 0.032 -36.0
6 0.016 -42.0
7 0.0078 -48.1