32.8.17 ADCON2

ADC Control Register 2
Note:
  1. To correctly calculate an average, the number of samples (set in RPT) must be 2CRS.
  2. CRS = 3’b111 is a reserved option.
  3. This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator selections, the delay may be many instructions.
  4. See the Computation Modes table for full mode descriptions.
Name: ADCON2
Offset: 0x113

Bit 76543210 
 PSISCRS[2:0]ACLRMD[2:0] 
Access R/WR/WR/WR/WR/W/HCR/WR/WR/W 
Reset 00000000 

Bit 7 – PSIS ADC Previous Sample Input Select bits

ValueDescription
1 FLTR is transferred to PREV at start of conversion
0 ADRES is transferred to PREV at start of conversion

Bits 6:4 – CRS[2:0] ADC Accumulated Calculation Right Shift Select bits

ValueNameDescription
111 - 000 MD = b’100’ Low-pass filter time constant is 2CRS, filter gain is 1:1
111 - 000 MD = b’011’ to b’001’ The accumulated value is right-shifted by CRS (divided by 2CRS)(1,2)
xxx MD = b’000’ to b’001’ These bits are ignored

Bit 3 – ACLR  A/D Accumulator Clear Command bit(3)

ValueDescription
1 The ACC, OV and CNT bits are cleared
0 Clearing action is complete (or not started)

Bits 2:0 – MD[2:0]  ADC Operating Mode Selection bits(4)

ValueDescription
111 - 101 Reserved
100 Low-Pass Filter mode
011 Burst Average mode
010 Average mode
001 Accumulate mode
000 Basic (Legacy) mode
To correctly calculate an average, the number of samples (set in RPT) must be 2CRS. CRS = 3’b111 is a reserved option. This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator selections, the delay may be many instructions. See the Computation Modes table for full mode descriptions.