33.3.1 Watchdog Timer Control Register

Legend: cfg = Configurable at Reset

Note:
  1. All these bits reflect the value of FWDT Configuration bits at Reset and can be set or cleared by software.
  2. When ON = 1, writes to the WINSIZE[1:0], RMPS[4:0], RMCLK[1:0], SMPS[4:0], WINDIS are disabled.
Table 33-2. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: WDTCON
Offset: 0x32C8

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 ONWINSIZE[1:0]RMPS[4:0] 
Access R/W-cfgR/W-cfgR/W-cfgR/W-cfgR/W-cfgR/W-cfgR/W-cfgR/W-cfg 
Reset  
Bit 76543210 
 RMCLK[1:0]SMPS[4:0]WINDIS 
Access R/W-cfgR/W-cfgR/W-cfgR/W-cfgR/W-cfgR/W-cfgR/W-cfgR/W-cfg 
Reset  

Bit 15 – ON  On bit(2)

ValueDescription
1Enables the WDT
0Disable and reset WDT

Bits 14:13 – WINSIZE[1:0] Size of Watchdog Window

ValueDescription
11Window size is 25% (Timer Count > 11xxx...xxxxx for timer to be cleared)
10Window size is 37.5% (Timer Count > 101xx...xxxxx for timer to be cleared)
01Window size is 50% (Timer Count > 1xxxx...xxxxx for timer to be cleared)
00Window size is 75% (Timer Count > 01xxx...xxxxx for timer to be cleared)

Bits 12:8 – RMPS[4:0] Configures the postscaler value for Run Mode Counter

Refer to Table 33-3 for the encoding of this bit field.

Bits 7:6 – RMCLK[1:0] Watchdog Timer Run Mode Counter Clock Selection bits

ValueDescription
11LPRC Oscillator
10BFRC Oscillator
01Reserved
00FOSC/4

Bits 5:1 – SMPS[4:0] Configures the postscaler value for Sleep Mode Counter

Refer to Table 33-3 for the encoding of this bit field.

Bit 0 – WINDIS Watchdog Window Mode Disable bit

ValueDescription
1Disables Window mode
0Enables Window mode