13.7.2 Interrupt Priority
Each peripheral interrupt source can be assigned to one of the seven priority levels. The user
assignable interrupt priority control bits for each individual interrupt are located in
the Least Significant three bits of each nibble within the IPCx registers. Bit 3 of each
nibble is not used and is read as a ‘0’. These bits define the priority
level assigned to a particular interrupt. The usable priority levels are one (lowest
priority) through seven (highest priority). If all the IPCx bits associated with an
interrupt source are cleared, the interrupt source is effectively disabled.
More than one interrupt request source can be assigned to a specific priority level. To resolve priority conflicts within a given user-assigned level, each source of an interrupt has a natural priority order based on its location in the IVT. The lower-numbered IRQ interrupt vectors have higher natural priority, while the higher-numbered vectors have lower natural priority (refer to Table 13-1 for IRQ numbers of interrupt). The overall priority level for any pending source of an interrupt is first determined by the user application-assigned priority of that source in the IPCx register, then by the natural order priority within the IVT/AIVT.
Natural order priority is used only to resolve conflicts between simultaneous pending interrupts with the same user application-assigned priority level. Once the priority conflict is resolved and the exception process begins, the CPU can be interrupted only by a source with a higher user application-assigned priority. Interrupts with the same user application-assigned priority, but a higher natural order priority, that become pending during the exception process remain pending until the current exception process completes.
Each interrupt source can be assigned to one of seven priority levels. This enables the user application to assign a low natural order priority and a very high overall priority level to an interrupt. For example, the UART1 RX Interrupt can be assigned to priority level seven, and the External Interrupt 0 (INT0) can be assigned to priority level one, thereby giving it a very low effective priority.