14.1 Device-Specific Information

Table 14-1. PORTA Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8							✔	✔
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
36-Pin	15:8
36-Pin	7:0		✔	✔	✔	✔	✔	✔	✔

Table 14-2. PORTB Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8							✔	✔
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
36-Pin	15:8
36-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔

Table 14-3. PORTC Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
36-Pin	15:8
36-Pin	7:0			✔	✔	✔	✔	✔	✔

Table 14-4. PORTD Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
64-Pin	15:8				✔	✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8								✔
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
36-Pin	15:8					✔
36-Pin	7:0				✔	✔	✔	✔	✔

Table 14-5. ANSELA Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
ANSELA	15:8					✔	✔	✔	✔
ANSELA	7:0	✔	✔	✔	✔	✔	✔	✔	✔
Note: ANSEL bit availability is dependent on existence of the port bit given a device variant as indicated in Table 14-1 through Table 14-4.

Table 14-6. ANSELB Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
ANSELB	15:8							✔	✔
ANSELB	7:0	✔	✔	✔	✔	✔	✔	✔	✔
Note: ANSEL bit availability is dependent on existence of the port bit given a device variant as indicated in Table 14-1 through Table 14-4.

Table 14-7. ANSELC Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
ANSELB	15:8
	7:0
Note: ANSEL bit availability is dependent on existence of the port bit given a device variant as indicated in Table 14-1 through Table 14-4.

Table 14-8. ANSELD Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
ANSELB	15:8
	7:0
Note: ANSEL bit availability is dependent on existence of the port bit given a device variant as indicated in Table 14-1 through Table 14-4.

Table 14-9. PPS Availability by Package
64-Pin	48-Pin	36-Pin
RP1-RP12	RP1-RP10	RP1-RP7
RP17-RP28	RP17-RP24	RP17-RP24
RP33-RP44	RP33-RP40	RP33-RP38
RP49-RP61	RP49-RP57	RP49-RP53

Table 14-10. Selectable Input Sources (Maps Input to Function)
Input Name⁽¹⁾	Function Name	Register	Register Bitfield
External Interrupt 1	INT1	RPINR0	INT1R[7:0]
External Interrupt 2	INT2	RPINR0	INT2R[7:0]
External Interrupt 3	INT3	RPINR0	INT3R[7:0]
External Interrupt 4	INT4	RPINR1	INT4R[7:0]
Timer1 External Clock	T1CK	RPINR1	T1CKR[7:0]
Reference Clock Input 1	REFI1	RPINR1	REFI1R[7:0]
Reference Clock Input 2	REFI2	RPINR1	REFI1R[7:0]
SCCP Input Capture 1	ICM1	RPINR2	ICM1R[7:0]
SCCP Input Capture 2	ICM2	RPINR2	ICM2R<7:0>
SCCP Input Capture 3	ICM3	RPINR2	ICM3R[7:0]
SCCP Input Capture 4	ICM4	RPINR2	ICM4R[7:0]
SCCP Fault A	OCFA	RPINR5	OCFAR[7:0]
SCCP Fault B	OCFB	RPINR5	OCFBR[7:0]
SCCP Fault C	OCFC	RPINR5	OCFCR[7:0]
SCCP Fault D	OCFD	RPINR5	OCFDR[7:0]
PWM Input 8	PCI8	RPINR6	PCI8R[7:0]
PWM Input 9	PCI9	RPINR6	PCI9R[7:0]
PWM Input 10	PCI10	RPINR6	PCI10R[7:0]
PWM Input 11	PCI11	RPINR6	PCI11R[7:0]
QEI1 Input A	QEIA1	RPINR7	QEIA1R[7:0]
QEI1 Input B	QEIB1	RPINR7	QEIB1R[7:0]
QEI Index 1 Input	QEINDX1	RPINR7	QEINDX1R[7:0]
QEI Home 1 Input	QEIHOM1	RPINR7	QEIHOM1R[7:0]
UART1 Receive	U1RX	RPINR9	U1RXR[7:0]
UART1 Data-Set-Ready	U1DSR	RPINR9	U1DSRR[7:0]
UART2 Receive	U2RX	RPINR9	U2RXR[7:0]
UART2 Data-Set-Ready	U2DSR	RPINR9	U2DSRR[7:0]
SPI1 Data Input	SDI1	RPINR10	SDI1R[7:0]
SPI1 Clock Input	SCK1IN	RPINR10	SCK1R[7:0]
SPI1 Client Select	SS1	RPINR10	SS1R[7:0]
SPI2 Data Input	SDI2	RPINR11	SDI2R[7:0]
SPI2 Clock Input	SCK2IN	RPINR11	SCK2R[7:0]
SPI2 Client Select	SS2	RPINR11	SS2R[7:0]
UART3 Receive	U3RX	RPINR13	U3RXR[7:0]
UART3 Data-Set-Ready	U3DSR	RPINR13	U3DSRR[7:0]
SENT1 Input	SENT1	RPINR14	SENT1R[7:0]
SENT2 Input	SENT2	RPINR14	SENT2R[7:0]
SPI3 Data Input	SDI3	RPINR15	SDI3R[7:0]
SPI3 Clock Input	SCK3IN	RPINR15	SCK3R[7:0]
SPI3 Client Select	SS3	RPINR15	SS3R[7:0]
PWM Input 12	PCI12	RPINR17	PCI12R[7:0]
PWM Input 13	PCI13	RPINR17	PCI13R[7:0]
PWM Input 12	PCI14	RPINR17	PCI17R[7:0]
PWM Input 15	PCI15	RPINR17	PCI17R[7:0]
PWM Input 16	PCI16	RPINR18	PCI16R[7:0]
PWM Input 17	PCI17	RPINR18	PCI17R[7:0]
PWM Input 18	PCI18	RPINR18	PCI18R[7:0]
ADC Trigger 31 Input	ADTRIG31	RPINR18	ADTRIG31R[7:0]
BiSS Return Input	BISS1SL	RPINR19	BISS1SLR[7:0]
BiSS Get Sense Input	BISS1GS	RPINR19	BISS1GSR[7:0]
CLC Input A	CLCINA	RPINR20	CLCINAR[7:0]
CLC Input B	CLCINB	RPINR20	CLCINBR[7:0]
CLC Input C	CLCINC	RPINR20	CLCINCR[7:0]
CLC Input D	CLCIND	RPINR20	CLCINDR[7:0]
UART1 Clear-to-Send	U1CTS	RPINR21	U1CTS[7:0]
UART2 Clear-to-Send	U2CTS	RPINR21	U2CTS[7:0]
UART3 Clear-to-Send	U3CTS	RPINR21	U3CTS[7:0]
Note: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

Table 14-11. Pin Correlation to Input Remap #⁽¹⁾
Index/Remap Input #	Function	Available on Ports
193	RPV15	Virtual RPV15
192	RPV14	Virtual RPV14
191	RPV13	Virtual RPV13
190	RPV12	Virtual RPV12
189	RPV11	Virtual RPV11
188	RPV10	Virtual RPV10
187	RPV9	Virtual RPV9
186	RPV8	Virtual RPV8
185	RPV7	Virtual RPV7
184	RPV6	Virtual RPV6
183	RPV5	Virtual RPV5
182	RPV4	Virtual RPV4
181	RPV3	Virtual RPV3
180	RPV2	Virtual RPV2
179	RPV1	Virtual RPV1
178	RPV0	Virtual RPV0
177	DAC3 pwm_req_off	Internal
176	DAC3 pwm_req_on	Internal
175	DAC2 pwm_req_off	Internal
174	DAC2 pwm_req_on	Internal
173	DAC1 pwm_req_off	Internal
172	DAC1 pwm_req_on	Internal
171	PEVTF	Internal
170	PEVTE	Internal
169	PEVTD	Internal
168	PTG TRIG[27]	Internal
167	PTG TRIG[26]	Internal
166-164	Reserved	—
163	CMP3	Internal
162	CMP2	Internal
161	CMP1	Internal
160-62	Reserved	—
61	RD12	Port Pin RD12
60	RD11	Port Pin RD11
59	RD10	Port Pin RD10
58	RD9	Port Pin RD9
57	RD8	Port Pin RD8
56	RD7	Port Pin RD7
55	RD6	Port Pin RD6
54	RD5	Port Pin RD5
53	RD4	Port Pin RD4
52	RD3	Port Pin RD3
51	RD2	Port Pin RD2
50	RD1	Port Pin RD1
49	RD0	Port Pin RD0
48-45	Reserved	—
44	RC11	Port Pin RC11
43	RC10	Port Pin RC10
42	RC9	Port Pin RC9
41	RC8	Port Pin RC8
40	RC7	Port Pin RC7
39	RC6	Port Pin RC6
38	RC5	Port Pin RC5
37	RC4	Port Pin RC4
36	RC3	Port Pin RC3
35	RC2	Port Pin RC2
34	RC1	Port Pin RC1
33	RC0	Port Pin RC0
32-29	Reserved	—
28	RB11	Port Pin RB11
27	RB10	Port Pin RB10
26	RB9	Port Pin RB9
25	RB8	Port Pin RB8
24	RB7	Port Pin RB7
23	RB6	Port Pin RB6
22	RB5	Port Pin RB5
21	RB4	Port Pin RB4
20	RB3	Port Pin RB3
19	RB2	Port Pin RB2
18	RB1	Port Pin RB1
17	RB0	Port Pin RB0
16-13	Reserved	—
12	RA11	Port Pin RA11
11	RA10	Port Pin RA10
10	RA9	Port Pin RA9
9	RA8	Port Pin RA8
8	RA7	Port Pin RA7
7	RA6	Port Pin RA6
6	RA5	Port Pin RA5
5	RA4	Port Pin RA4
4	RA3	Port Pin RA3
3	RA2	Port Pin RA2
2	RA1	Port Pin RA1
1	RA0	Port Pin RA0
0	Tied to 1’b0	—
Note: This list of output signals can be mapped to any of the peripheral inputs listed in Table 14-10.

Table 14-12. Virtual Outputs to Remappable Output Registers⁽¹⁾
Virtual Outputs	Remappable Output Register	Register Bitfield
RPV0	RPOR16	RP65R[6:0]
RPV1	RPOR16	RP66R[6:0]
RPV2	RPOR16	RP67R[6:0]
RPV3	RPOR16	RP68R[6:0]
RPV4	RPOR17	RP69R[6:0]
RPV5	RPOR17	RP70R[6:0]
RPV6	RPOR17	RP71R[6:0]
RPV7	RPOR17	RP72R[6:0]
RPV8	RPOR18	RP73R[6:0]
RPV9	RPOR18	RP74R[6:0]
RPV10	RPOR18	RP75R[6:0]
RPV11	RPOR18	RP76R[6:0]
RPV12	RPOR19	RP77R[6:0]
RPV13	RPOR19	RP78R[6:0]
RPV14	RPOR19	RP79R[6:0]
RPV15	RPOR19	RP80R[6:0]
Note: This list of virtual output signals can be mapped to any of the peripheral inputs listed in Table 14-10.

Table 14-13. Output Selection for Remappable Pins (RPn)
Function	RPnR[5:0]	Output Name
Default PORT	0	RPn tied to Default Pin
PWM1H	1	RPn tied to PWM1H Output
PWM1L	2	RPn tied to PWM1L Output
PWM2H	3	RPn tied to PWM2H Output
PWM2L	4	RPn tied to PWM2L Output
PWM3H	5	RPn tied to PWM3H Output
PWM3L	6	RPn tied to PWM3L Output
PWM4H	7	RPn tied to PWM4H Output
PWM4L	8	RPn tied to PWM4L Output
U1TX	9	RPn tied to UART1 Transmit
U1RTS	10	RPn tied to UART1 Request-to-Send
U2TX	11	RPn tied to UART2 Transmit
U2RTS	12	RPn tied to UART2 Request-to-Send
SDO1	13	RPn tied to SPI1 Data Output
SCK1OUT	14	RPn tied to SPI1 Clock Output
SS1OUT	15	RPn tied to SPI1 Client Select
SDO2	16	RPn tied to SPI2 Data Output
SCK2OUT	17	RPn tied to SPI2 Clock Output
SS2OUT	18	RPn tied to SPI2 Client Select
SDO3	19	RPn tied to SPI3 Data Output
SCK3OUT	20	RPn tied to SPI3 Clock Output
SS3OUT	21	RPn tied to SPI3 Client Select
REFO1	22	RPn tied to Reference Clock 1 Output
REFO2	23	RPn tied to Reference Clock 2 Output
OCM1	24	RPn tied to CCP1 Output Compare Event
OCM2	25	RPn tied to CCP2 Output Compare Event
OCM3	26	RPn tied to CCP3 Output Compare Event
OCM4	27	RPn tied to CCP4 Enable Output Compare Event
CMP1	32	RPn tied to Comparator 1 Output
CMP2	33	RPn tied to Comparator 2 Output
CMP3	34	RPn tied to Comparator 2 Output
U3TX	36	RPn tied to UART3 Transmit
U3RTS	37	RPn tied to UART Request-to-Send
PEVTA	43	RPn tied to PWM Event A Output
PEVTB	44	RPn tied to PWM Event B output
QEICMP1	45	RPn tied to QEI Comparator 1 Output
CLC1OUT	47	RPn tied to CLC1 Output
CLC2OUT	48	RPn tied to CLC2 Output
PEVTC	51	RPn tied to PWM Event C Output
PEVTD	52	RPn tied to PWM Event D Output
PEVTE	53	RPn tied to PWM Event E Output
PEVTF	54	RPn tied to PWM Event F Output
PTG TRIG 24	55	RPn tied to PTG Trigger 24 Output
PTG TRIG 25	56	RPn tied to PTG Trigger 25 Output
SENT1OUT	57	RPn tied to SENT1 Output
SENT2OUT	58	RPn tied to SENT2 Output
BISS1MO	63	RPn tied to BiSS Output
BISS1MA	64	RPn tied to BiSS CLK
CLC3OUT	65	RPn tied to CLC3 Output
CLC4OUT	66	RPn tied to CLC4 Output
U1DTRn	67	RPn tied to UART1 Data Terminal Ready Output
U2DTRn	68	RPn tied to UART2 Data Terminal Ready Output
U3DTRn	69	RPn tied to UART3 Data Terminal Ready Output