14.3 Register Summary

Note: SFR bit availability is defined in Table 14-1 through Table 14-4 for each device variant and port, respectively.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00 ... 0x01FF	Reserved
0x0200	PORTA	7:0	PORTA[7:0]
		15:8	PORTA[15:8]
		23:16	ALTPORTA[7:0]
		31:24	ALTPORTA[15:8]
0x0204	LATA	7:0	LATA[7:0]
		15:8	LATA[15:8]
		23:16	ALTLATA[7:0]
		31:24	ALTLATA[15:8]
0x0208	TRISA	7:0	TRISA[7:0]
		15:8	TRISA[15:8]
		23:16	ALTTRISA[7:0]
		31:24	ALTTRISA[15:8]
0x020C	CNSTATA	7:0	CNSTATA[7:0]
		15:8	CNSTATA[15:8]
		23:16	CNSTATA[7:0]
		31:24	CNSTATA[15:8]
0x0210	CNFA	7:0	CNFA[7:0]
		15:8	CNFA[15:8]
		23:16	ALTCNFA[7:0]
		31:24	ALTCNFA[15:8]
0x0214	PORTB	7:0	PORTB[7:0]
		15:8	PORTB[15:8]
		23:16	ALTPORTB[7:0]
		31:24	ALTPORTB[15:8]
0x0218	LATB	7:0	LATB[7:0]
		15:8	LATB[15:8]
		23:16	ALTLATB[7:0]
		31:24	ALTLATB[15:8]
0x021C	TRISB	7:0	TRISB[7:0]
		15:8	TRISB[15:8]
		23:16	ALTTRISB[7:0]
		31:24	ALTTRISB[15:8]
0x0220	CNSTATB	7:0	CNSTATB[7:0]
		15:8	CNSTATB[15:8]
		23:16	CNSTATB[7:0]
		31:24	CNSTATB[15:8]
0x0224	CNFB	7:0	CNFB[7:0]
		15:8	CNFB[15:8]
		23:16	ALTCNFB[7:0]
		31:24	ALTCNFB[15:8]
0x0228	PORTC	7:0	PORTC[7:0]
		15:8	PORTC[15:8]
		23:16	ALTPORTC[7:0]
		31:24	ALTPORTC[15:8]
0x022C	LATC	7:0	LATC[7:0]
		15:8	LATC[15:8]
		23:16	ALTLATC[7:0]
		31:24	ALTLATC[15:8]
0x0230	TRISC	7:0	TRISC[7:0]
		15:8	TRISC[15:8]
		23:16	ALTTRISC[7:0]
		31:24	ALTTRISC[15:8]
0x0234	CNSTATC	7:0	CNSTATC[7:0]
		15:8	CNSTATC[15:8]
		23:16	CNSTATC[7:0]
		31:24	CNSTATC[15:8]
0x0238	CNFC	7:0	CNFC[7:0]
		15:8	CNFC[15:8]
		23:16	ALTCNFC[7:0]
		31:24	ALTCNFC[15:8]
0x023C	PORTD	7:0	PORTD[7:0]
		15:8	PORTD[15:8]
		23:16	ALTPORTD[7:0]
		31:24	ALTPORTD[15:8]
0x0240	LATD	7:0	LATD[7:0]
		15:8	LATD[15:8]
		23:16	ALTLATD[7:0]
		31:24	ALTLATD[15:8]
0x0244	TRISD	7:0	TRISD[7:0]
		15:8	TRISD[15:8]
		23:16	ALTTRISD[7:0]
		31:24	ALTTRISD[15:8]
0x0248	CNSTATD	7:0	CNSTATD[7:0]
		15:8	CNSTATD[15:8]
		23:16	CNSTATD[7:0]
		31:24	CNSTATD[15:8]
0x024C	CNFD	7:0	CNFD[7:0]
		15:8	CNFD[15:8]
		23:16	ALTCNFD[7:0]
		31:24	ALTCNFD[15:8]
0x0250 ... 0x1E8F	Reserved
0x1E90	IOIM1CON	7:0	FBKSEL[3:0]				REFSEL[3:0]
		15:8	ON		SLPEN	SIDL		EXTCLK
		23:16	EOVFV[7:0]
		31:24					FLTINJ	OKINJ	ATEST[1:0]
0x1E94	IOIM1BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1E98	IOIM1STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1E9C	IOIM2CON	7:0	FBKSEL[3:0]				REFSEL[3:0]
		15:8	ON		SLPEN	SIDL		EXTCLK
		23:16	EOVFV[7:0]
		31:24					FLTINJ	OKINJ	ATEST[1:0]
0x1EA0	IOIM2BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1EA4	IOIM2STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1EA8	IOIM3CON	7:0	FBKSEL[3:0]				REFSEL[3:0]
		15:8	ON		SLPEN	SIDL		EXTCLK
		23:16	EOVFV[7:0]
		31:24					FLTINJ	OKINJ	ATEST[1:0]
0x1EAC	IOIM3BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1EB0	IOIM3STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1EB4	IOIM4CON	7:0	FBKSEL[3:0]				REFSEL[3:0]
		15:8	ON		SLPEN	SIDL		EXTCLK
		23:16	EOVFV[7:0]
		31:24					FLTINJ	OKINJ	ATEST[1:0]
0x1EB8	IOIM4BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1EBC	IOIM4STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1EC0 ... 0x1EC3	Reserved
0x1EC4	IOIM5BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1EC8	IOIM5STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1ECC ... 0x1ECF	Reserved
0x1ED0	IOIM6BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1ED4	IOIM6STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1ED8 ... 0x1EDB	Reserved
0x1EDC	IOIM7BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1EE0	IOIM7STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1EE4 ... 0x1EE7	Reserved
0x1EE8	IOIM8BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1EEC	IOIM8STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1EF0 ... 0x1EF3	Reserved
0x1EF4	IOIM9BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1EF8	IOIM9STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1EFC ... 0x1EFF	Reserved
0x1F00	IOIM10BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1F04	IOIM10STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1F08 ... 0x1F0B	Reserved
0x1F0C	IOIM11BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1F10	IOIM11STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1F14 ... 0x1F17	Reserved
0x1F18	IOIM12BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1F1C	IOIM12STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1F20 ... 0x1F23	Reserved
0x1F24	IOIM13BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1F28	IOIM13STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1F2C ... 0x1F2F	Reserved
0x1F30	IOIM14BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1F34	IOIM14STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1F38 ... 0x1F3B	Reserved
0x1F3C	IOIM15BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1F40	IOIM15STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1F44 ... 0x1F47	Reserved
0x1F48	IOIM16BCON	7:0	BLANK[7:0]
		15:8	BLANK[15:8]
		23:16
		31:24
0x1F4C	IOIM16STAT	7:0	FFEDGE	FREDGE	RFEDGE	RREDGE		OVF	ERR	OK
		15:8	ERRCNT[7:0]
		23:16
		31:24
0x1F50 ... 0x363F	Reserved
0x3640	ANSELA	7:0	ANSELA[7:0]
		15:8	ANSELA[15:8]
		23:16	ALTANSELA[7:0]
		31:24	ALTANSELA[15:8]
0x3644	ODCA	7:0	ODCA[7:0]
		15:8	ODCA[15:8]
		23:16	ALTODCA[7:0]
		31:24	ALTODCA[15:8]
0x3648	CNPUA	7:0	CNPUA[7:0]
		15:8	CNPUA[15:8]
		23:16	ALTCNPUA[7:0]
		31:24	ALTCNPUA[15:8]
0x364C	CNPDA	7:0	CNPDA[7:0]
		15:8	CNPDA[15:8]
		23:16	ALTCNPDA[7:0]
		31:24	ALTCNPDA[15:8]
0x3650	CNCONA	7:0
		15:8	ON				CNSTYLE	PORT32
		23:16
		31:24
0x3654	CNEN0A	7:0	CNEN0A[7:0]
		15:8	CNEN0A[15:8]
		23:16	ALTCNEN0A[7:0]
		31:24	ALTCNEN0A[15:8]
0x3658	CNEN1A	7:0	CNEN1A[7:0]
		15:8	CNEN1A[15:8]
		23:16	ALTCNEN1A[7:0]
		31:24	ALTCNEN1A[15:8]
0x365C ... 0x3663	Reserved
0x3664	ANSELB	7:0	ANSELB[7:0]
		15:8	ANSELB[15:8]
		23:16	ALTANSELB[7:0]
		31:24	ALTANSELB[15:8]
0x3668	ODCB	7:0	ODCB[7:0]
		15:8	ODCB[15:8]
		23:16	ALTODCB[7:0]
		31:24	ALTODCB[15:8]
0x366C	CNPUB	7:0	CNPUB[7:0]
		15:8	CNPUB[15:8]
		23:16	ALTCNPUB[7:0]
		31:24	ALTCNPUB[15:8]
0x3670	CNPDB	7:0	CNPDB[7:0]
		15:8	CNPDB[15:8]
		23:16	ALTCNPDB[7:0]
		31:24	ALTCNPDB[15:8]
0x3674	CNCONB	7:0
		15:8	ON				CNSTYLE	PORT32
		23:16
		31:24
0x3678	CNEN0B	7:0	CNEN0B[7:0]
		15:8	CNEN0B[15:8]
		23:16	ALTCNEN0B[7:0]
		31:24	ALTCNEN0B[15:8]
0x367C	CNEN1B	7:0	CNEN1B[7:0]
		15:8	CNEN1B[15:8]
		23:16	ALTCNEN1B[7:0]
		31:24	ALTCNEN1B[15:8]
0x3680 ... 0x368B	Reserved
0x368C	ODCC	7:0	ODCC[7:0]
		15:8	ODCC[15:8]
		23:16	ALTODCC[7:0]
		31:24	ALTODCC[15:8]
0x3690	CNPUC	7:0	CNPUC[7:0]
		15:8	CNPUC[15:8]
		23:16	ALTCNPUC[7:0]
		31:24	ALTCNPUC[15:8]
0x3694	CNPDC	7:0	CNPDC[7:0]
		15:8	CNPDC[15:8]
		23:16	ALTCNPDC[7:0]
		31:24	ALTCNPDC[15:8]
0x3698	CNCONC	7:0
		15:8	ON				CNSTYLE	PORT32
		23:16
		31:24
0x369C	CNEN0C	7:0	CNEN0C[7:0]
		15:8	CNEN0C[15:8]
		23:16	ALTCNEN0C[7:0]
		31:24	ALTCNEN0C[15:8]
0x36A0	CNEN1C	7:0	CNEN1C[7:0]
		15:8	CNEN1C[15:8]
		23:16	ALTCNEN1C[7:0]
		31:24	ALTCNEN1C[15:8]
0x36A4 ... 0x36AF	Reserved
0x36B0	ODCD	7:0	ODCD[7:0]
		15:8	ODCD[15:8]
		23:16	ALTODCD[7:0]
		31:24	ALTODCD[15:8]
0x36B4	CNPUD	7:0	CNPUD[7:0]
		15:8	CNPUD[15:8]
		23:16	ALTCNPUD[7:0]
		31:24	ALTCNPUD[15:8]
0x36B8	CNPDD	7:0	CNPDD[7:0]
		15:8	CNPDD[15:8]
		23:16	ALTCNPDD[7:0]
		31:24	ALTCNPDD[15:8]
0x36BC	CNCOND	7:0
		15:8	ON				CNSTYLE	PORT32
		23:16
		31:24
0x36C0	CNEN0D	7:0	CNEN0D[7:0]
		15:8	CNEN0D[15:8]
		23:16	ALTCNEN0D[7:0]
		31:24	ALTCNEN0D[15:8]
0x36C4	CNEN1D	7:0	CNEN1D[7:0]
		15:8	CNEN1D[15:8]
		23:16	ALTCNEN1D[7:0]
		31:24	ALTCNEN1D[15:8]
0x36C8 ... 0x38FF	Reserved
0x3900	RPCON	7:0
		15:8					IOLOCK
		23:16
		31:24
0x3904	RPINR0	7:0
		15:8	INT1R[7:0]
		23:16	INT2R[7:0]
		31:24	INT3R[7:0]
0x3908	RPINR1	7:0	INT4R[7:0]
		15:8	T1CKR[7:0]
		23:16	REFI1R[7:0]
		31:24	REFI2R[7:0]
0x390C	RPINR2	7:0	ICM1R[7:0]
		15:8	ICM2R[7:0]
		23:16	ICM3R[7:0]
		31:24	ICM4R[7:0]
0x3910 ... 0x3911	Reserved
0x3912	RPINR4	7:0	TCKI2R[7:0]
		15:8	ICM2R[7:0]
		23:16
		31:24
0x3916 ... 0x3917	Reserved
0x3918	RPINR5	7:0	OCFA[7:0]
		15:8	OCFB[7:0]
		23:16	OCFCR[7:0]
		31:24	OCFDR[7:0]
0x391C	RPINR6	7:0	PCI8R[7:0]
		15:8	PCI9R[7:0]
		23:16	PCI10R[7:0]
		31:24	PCI11R[7:0]
0x3920	RPINR7	7:0	QEIA1R[7:0]
		15:8	QEIB1R[7:0]
		23:16	QEIINDX1R[7:0]
		31:24	QEIHOME1R[7:0]
0x3924 ... 0x3927	Reserved
0x3928	RPINR9	7:0	U1RXR[7:0]
		15:8	U1CTSR[7:0]
		23:16	U2RXR[7:0]
		31:24	U2CTSR[7:0]
0x392C	RPINR10	7:0	SDI1R[7:0]
		15:8	SCK1R[7:0]
		23:16	SS1R[7:0]
		31:24
0x3930	RPINR11	7:0	SDI2R[7:0]
		15:8	SCK2R[7:0]
		23:16	SS2R[7:0]
		31:24
0x3934 ... 0x3937	Reserved
0x3938	RPINR13	7:0	U3RXR[7:0]
		15:8	U3CTSR[7:0]
		23:16
		31:24
0x393C	RPINR14	7:0
		15:8
		23:16	SENT1R[7:0]
		31:24	SENT2R[7:0]
0x3940	RPINR15	7:0	SDI3R[7:0]
		15:8	SCK3R[7:0]
		23:16	SS3R[7:0]
		31:24
0x3944 ... 0x3947	Reserved
0x3948	RPINR17	7:0	PCI12R[7:0]
		15:8	PCI13R[7:0]
		23:16	PCI14R[7:0]
		31:24	PCI15R[7:0]
0x394C	RPINR18	7:0	PCI16R[7:0]
		15:8	PCI17R[7:0]
		23:16	PCI18R[7:0]
		31:24	ADTRIG31R[7:0]
0x3950	RPINR19	7:0	BISS1SLR[7:0]
		15:8	BISS1GSR[7:0]
		23:16
		31:24
0x3954	RPINR20	7:0	CLCINAR[7:0]
		15:8	CLCINBR[7:0]
		23:16	CLCINCR[7:0]
		31:24	CLCINDR[7:0]
0x3958	RPINR21	7:0	U1DCDR[7:0]
		15:8	U2DCDR[7:0]
		23:16	U3DCDR[7:0]
		31:24
0x395C ... 0x397F	Reserved
0x3980	RPOR0	7:0		RP1R[6:0]
		15:8		RP2R[6:0]
		23:16		RP3R[6:0]
		31:24		RP4R[6:0]
0x3984	RPOR1	7:0		RP5R[6:0]
		15:8		RP6R[6:0]
		23:16		RP7R[6:0]
		31:24		RP8R[6:0]
0x3988	RPOR2	7:0		RP9R[6:0]
		15:8		RP10R[6:0]
		23:16		RP11R[6:0]
		31:24		RP12R[6:0]
0x398C	RPOR3	7:0			RP38R[5:0]
		15:8			RP39R[5:0]
		23:16
		31:24
0x3990	RPOR4	7:0		RP17R[6:0]
		15:8		RP18R[6:0]
		23:16		RP19R[6:0]
		31:24		RP20R[6:0]
0x3994	RPOR5	7:0		RP21R[6:0]
		15:8		RP22R[6:0]
		23:16		RP23R[6:0]
		31:24		RP24R[6:0]
0x3998	RPOR6	7:0		RP25R[6:0]
		15:8		RP26R[6:0]
		23:16		RP27R[6:0]
		31:24		RP28R[6:0]
0x399C	RPOR7	7:0			RP46R[5:0]
		15:8			RP47R[5:0]
		23:16
		31:24
0x39A0	RPOR8	7:0		RP33R[6:0]
		15:8		RP34R[6:0]
		23:16		RP35R[6:0]
		31:24		RP36R[6:0]
0x39A4	RPOR9	7:0		RP37R[6:0]
		15:8		RP38R[6:0]
		23:16		RP39R[6:0]
		31:24		RP40R[6:0]
0x39A8	RPOR10	7:0		RP41R[6:0]
		15:8		RP42R[6:0]
		23:16		RP43R[6:0]
		31:24		RP44R[6:0]
0x39AC	RPOR11	7:0			RP54R[5:0]
		15:8			RP55R[5:0]
		23:16
		31:24
0x39B0	RPOR12	7:0		RP49R[6:0]
		15:8		RP50R[6:0]
		23:16		RP51R[6:0]
		31:24		RP52R[6:0]
0x39B4	RPOR13	7:0		RP53R[6:0]
		15:8		RP54R[6:0]
		23:16		RP55R[6:0]
		31:24		RP56R[6:0]
0x39B8	RPOR14	7:0		RP57R[6:0]
		15:8		RP58R[6:0]
		23:16		RP59R[6:0]
		31:24		RP60R[6:0]
0x39BC	RPOR15	7:0		RP61R[6:0]
		15:8
		23:16
		31:24
0x39C0	RPOR16	7:0		RP65R[6:0]
		15:8		RP66R[6:0]
		23:16		RP67R[6:0]
		31:24		RP68R[6:0]
0x39C4	RPOR17	7:0		RP69R[6:0]
		15:8		RP70R[6:0]
		23:16		RP71R[6:0]
		31:24		RP72R[6:0]
0x39C8	RPOR18	7:0		RP73R[6:0]
		15:8		RP74R[6:0]
		23:16		RP75R[6:0]
		31:24		RP76R[6:0]
0x39CC	RPOR19	7:0		RP76R[6:0]
		15:8		RP78R[6:0]
		23:16		RP79R[6:0]
		31:24		RP80R[6:0]