17.4.2.9.1 ADC Triggers

Each PWM Generator has the capability to trigger multiple ADCs, either internal or external to the device. ADC Triggers are based on the TRIGA, TRIGB and TRIGC compare events for timing within the PWM cycle. The ADC Triggers are also used as triggers for other peripherals and functions, such as the PTG, DAC and interrupts. The ADC Triggers are also made available externally through the Event Output block (see PWM Event Outputs) or internally in conjunction with the CPU interrupt controller.

Multiple TRIGx sources may be enabled to create the ADC Trigger output, and when enabled, they are logically OR’d together. If the multiple TRIGx registers are enabled to produce ADC Trigger events, they must be configured to allow unique trigger events to the ADC.

Each PWM Generator can generate two ADC Triggers: ADC Trigger 1 and ADC Trigger 2. The two trigger outputs are useful for SMPS applications, where it is often desirable to measure two quantities in a single cycle. Each trigger is connected to a separate ADC, or possibly, a separate ADC Trigger input. The ADC Trigger 1 output has an additional offset and postscaler function to allow these functions:

• Postscaler, to reduce the frequency of ADC Trigger events.
• Offset, a one-time offset may be applied to ADC Trigger events. This allows postscaled 
trigger events to be interleaved with trigger events from other PWM Generators.

Trigger events from ADC Trigger 2 will be produced every PWM cycle. ADC Trigger 1 output may be postscaled using the ADTR1PS[4:0] control bits (PGxEVT[15:11]) to reduce the frequency of ADC conversions. In addition, the ADC Trigger 1 output can be offset by a certain number of trigger events using the ADTR1OFS[4:0] control bits (PGxEVT[20:16]). Together, these two sets of control bits allow the user to establish an interleaved set of ADC Triggers from multiple PWM Generators. In addition, ADC Trigger events may be simply postscaled to reduce the frequency of ADC measurements. If the ADTR1PS[4:0] control bits are set to ‘00000’, an ADC Trigger event will be produced on every PWM cycle. When these control bits are set to a non-zero value, an ADC Trigger will be produced during the PWM cycle after the ON bit is set and every N cycle thereafter. The ADTR1OFS[4:0] bits value establishes a one-time offset of 0 to 15 trigger events after the ON bit has been set. After this offset has been established, the trigger postscaler will begin to count the number of trigger events determined by the ADTR1PS[4:0] bits value. When interleaving ADC Triggers from multiple PWM Generators, all PWM Generators should be programmed to have the same period to ensure consistent spacing between the trigger events.