7.3.9 BMX Error Status Register for ICD
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | BMXICDERR |
| Offset: | 0x790 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DBGWERR | |||||||||
| Access | R/HS/C | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| IRAMWERR | ADDWERR | BADTGTWERR | |||||||
| Access | R/HS/C | R/HS/C | R/HS/C | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DBGRERR | YRAMRERR | XRAMRERR | |||||||
| Access | R/HS/C | R/HS/C | R/HS/C | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IRAMRDERR | ADDRERR | BADTGTRERR | |||||||
| Access | R/HS/C | R/HS/C | R/HS/C | ||||||
| Reset | 0 | 0 | 0 |
Bit 28 – DBGWERR Debug RAM Write Error bit
| Value | Description |
|---|---|
1 | Bus error generated by debug RAM write operation |
0 | No error on debug RAM write operation |
Bit 18 – IRAMWERR IRAM Write Error Flag bit
| Value | Description |
|---|---|
1 | Error generated by invalid instruction write outside of IRAM space |
0 | No IRAM write address errors |
Bit 17 – ADDWERR Invalid Address Write Error Flag bit
| Value | Description |
|---|---|
1 | Error generated by read or write to invalid address space |
0 | No unimplemented address write error |
Bit 16 – BADTGTWERR Invalid Target Write Error Flag bit
| Value | Description |
|---|---|
1 | Error generated by write to disallowed target space |
0 | No invalid target write error |
Bit 12 – DBGRERR Debug RAM Read Error bit
| Value | Description |
|---|---|
1 | Bus error generated by debug RAM read operation |
0 | No error on debug RAM read operation |
Bit 11 – YRAMRERR YRAM Read Error Flag bits
| Value | Description |
|---|---|
1 | Bus error generated by YRAM read operation |
0 | No error on YRAM read operation |
Bit 10 – XRAMRERR XRAM Read Error Flag bits
| Value | Description |
|---|---|
1 | Bus error generated by XRAM read operation |
0 | No error on XRAM read operation |
Bit 2 – IRAMRDERR IRAM Read Error Flag bit
| Value | Description |
|---|---|
1 | Error generated by invalid instruction read outside of IRAM space |
0 | No IRAM read address errors |
Bit 1 – ADDRERR Invalid Address Error Flag bit
| Value | Description |
|---|---|
1 | Error generated by read or write to invalid address space |
0 | No unimplemented address write error |
Bit 0 – BADTGTRERR Invalid Target Read Error Flag bit
| Value | Description |
|---|---|
1 | Error generated by read to disallowed target space |
0 | No invalid target error |