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7.3.2 BMX Instruction RAM Low Address
Register
Table 7-4. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable
bit HC Cleared by
Hardware (Gray
cell) Unimplemented W Writable
bit HS Set by
Hardware X Bit is unknown
at Reset C Write to
clear S Software
settable bit x Channel
number
Name: BMXIRAML Offset: 0x774
Bit 31 30 29 28 27 26 25 24 BMXIRAML[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 BMXIRAML[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 BMXIRAML[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 BMXIRAML[7:2] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0
Bits 31:24 – BMXIRAML[31:24] Lower Boundary
Address for Instruction RAM bits Defines the lower
boundary address (inclusive) for instruction RAM.
Bits 23:16 – BMXIRAML[23:16] Lower Boundary Address for Instruction RAM
bits
Bits 15:8 – BMXIRAML[15:8] Lower Boundary Address for Instruction RAM
bits
Bits 7:2 – BMXIRAML[7:2] Lower Boundary Address for Instruction RAM
bits
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