7.3.1 Bus Initiator Priority Control Register
Note:
- CPU has the highest priority.
- The ICD does not have an associated INITPR bit and is always forced to the lowest priority.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | BMXINITPR |
| Offset: | 0x770 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NVMPR | DMAPR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – NVMPR NVM Priority Override bit
| Value | Description |
|---|---|
1 | Raise NVM initiator RAM access above CPU |
0 | No change to NVM initiator RAM access priority |
Bit 0 – DMAPR DMA Priority Override bit
| Value | Description |
|---|---|
1 | Raise DMA initiator RAM access above CPU |
0 | No change to DMA initiator RAM access priority |