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7.3.3 BMX Instruction RAM High Address
Register
Table 7-5. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable
bit HC Cleared by
Hardware (Gray
cell) Unimplemented W Writable
bit HS Set by
Hardware X Bit is unknown
at Reset C Write to
clear S Software
settable bit x Channel
number
Name: BMXIRAMH Offset: 0x778
Bit 31 30 29 28 27 26 25 24 BMXIRAMH[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 BMXIRAMH[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 BMXIRAMH[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 BMXIRAMH[7:2] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0
Bits 31:24 – BMXIRAMH[31:24] Upper Boundary
Address for Instruction RAM bits Defines the upper
boundary address (non-inclusive) for instruction RAM.
Bits 23:16 – BMXIRAMH[23:16] Upper Boundary Address for Instruction RAM
bits
Bits 15:8 – BMXIRAMH[15:8] Upper Boundary Address for Instruction RAM
bits
Bits 7:2 – BMXIRAMH[7:2] Upper Boundary Address for Instruction RAM
bits
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