27.4.5.2 Auxiliary Output Signal
The CCP modules can also generate a secondary output that is different from the CCP Sync
signal (or its alternate version if ALTSYNC is set). The auxiliary output is intended to
allow other digital peripherals to access internal CCP module signals, such as:
- Time Base Synchronization
- Peripheral Trigger and Clock Inputs
- Signal Gating
The type of output signal is selected using the AUXOUT[1:0] control bits (CCPxCON2[20:19]) and is dependent on the module operating mode. More options are available for each mode than with the alternate Sync output, as shown in Table 27-19.
| AUXOUT[1:0] | CCSEL | MOD[3:0] | Output Signal |
|---|---|---|---|
00 | x | xxxx | Disabled (no output) |
01 | 0 | ‘0000’ (Timer modes) | Time Base Period Reset or Rollover |
10 | Special Event Trigger Output | ||
11 | No Output | ||
01 | 0 | ‘0001’ through ‘1111’
(Output Compare modes) | Time Base Period Reset or Rollover |
10 | Output Compare Event Signal | ||
11 | Output Compare Signal | ||
01 | 1 | ‘xxxx’ (Input Capture modes) | Time Base Period Reset or Rollover |
10 | Reflects the Value of the CDIS Bit | ||
11 | Input Capture Event Signal |