21.4.2.1.2 Asynchronous Receive

The receiver block diagram of the UART module is illustrated in Figure 21-9. The important part of the receiver is the UARTx Receive (Serial) Shift Register (UxRSR). The data is received on the UxRX pin. After sampling the UxRX pin for the Stop bit, the received data in the UxRSR register is transferred to the receive FIFO, if it is empty.

Note: The UxRSR register is not mapped in data memory, so it is not available to the user application.

The reception is enabled by setting the RXEN bit (UxCON[4]). Clearing the RXEN bit causes the receive shifter to stop. As a consequence, RXIDL (UxSTAT[19]) is set to ‘1’.

Figure 21-9. Asynchronous Receiver Block Diagram

Note: ‘x’ denotes the UART number.