27.4.6.2 Timer Triggered Operation

Triggered operation of the timer is enabled when TRIGEN = 1. Triggered mode operation is useful in creating time delays. A pulse or edge event can be generated after the delay, depending on the module operating mode.

When configured for triggered operation, the module timer is held in Reset until a trigger event with the source selected by SYNC[4:0] occurs. After the trigger event occurs, the timer begins to count. The timer increments on every positive clock of the time base signal.

If the timer is configured for 16-bit dual timer operation (T32 = 0), only the timer based on CCPxTMRL will function in triggered operation. The timer, based on CCPxTMRH, will operate as a free-running timer.

The CCPTRIG status bit (CCPxSTAT[7]) indicates whether the timer is held in Reset or released to count. When CCPTRIG = 0, the timer is being held in Reset; when CCPTRIG = 1, the timer has been released.

There are two types of trigger conditions when operating in Triggered mode: Hardware/Software and Software-Only. Hardware/software triggered operation is shown in Figure 27-27. When the module is enabled for a triggered response, the timer is held in Reset. It remains in this state until a trigger event is asserted for the SYNC[4:0] input, which sets the CCPTRIG bit within two clock cycles. The trigger signal determines only when the time base starts counting; the CCPxPR register sets the period for the timer. Unlike Sync operation, all trigger sources available through the SYNC[4:0] bits may be used for triggered operation.

CCPTRIG can be manually set at any time and the timer can be released from Reset by writing a ‘1’ to the TRSET bit (CCPxSTAT[6]). The CCPTRIG bit can also be manually cleared in software by writing a ‘1’ to the TRCLR bit (CCPxSTAT[5]).

Software-Only operation is selected when SYNC[4:0] = 11111. In this configuration, the only way that the CCPTRIG bit can be set is by a software write to the TRSET bit. This selection effectively disables all external hardware trigger sources.

When the TRIGEN bit is cleared in software, the timer is reset to 0000h on the next timer clock rising edge and is ready for another SYNC[4:0].

Note: The TRSET and TRCLR bits are write-only bits which always read as ‘0’. Writing ‘0’ to either location has no effect.

The procedure for configuring the module for triggered operation is shown in Setup for Timer Triggered Operation (16-Bit Dual Timer Mode).

Figure 27-27. Timing for Triggered Operation (Hardware/Software Operations)

Setup for Timer Triggered Operation (16-Bit Dual Timer Mode)

CCP1CON1bits.TRIGEN=1;       // Set Sync/Triggered mode (Triggered Mode)
CCP1CON1bits.SYNC = 0x08;    // INT0 as trigger (verify the device
                              // for Trigger source)
CCP1CON1bits.T32=0;          // 16 bit dual timer mode
CCP1CON1bits.TMRSYNC = 0;    // Set timebase synchronization (Synchronized)
CCP1CON1bits.CLKSEL = 0;     // Set the clock source (Tcy)
CCP1CON1bits.TMRPS = 0;      // Set the clock pre-scaler (1:1)
CCP1PR = 0x00000FFF;         // 32-bit CCP period register
CCP1CON1bits.CCPON=1;        // Enable the Timer