13.8.2 Interrupt Nesting

Interrupts are nestable by default. Any ISR in progress can be interrupted by another source of interrupt with a higher user application-assigned priority level. Interrupt nesting can be disabled by setting the Interrupt Nesting Disable bit (NSTDIS) in the INTCON1 register. When the NSTDIS control bit is set, all interrupts in progress force the CPU priority to Level 7 by setting IPL = 0b111. This action effectively masks all other sources of interrupt until a RETFIE instruction is executed. When interrupt nesting is disabled, the user application-assigned IPLs have no effect except to resolve conflicts between simultaneous pending interrupts. The IPL bits (SR) become read-only when interrupt nesting is disabled. This prevents the user application from setting IPL to a lower value, which would effectively re-enable interrupt nesting.