17.4.2.10.3 Time Base Capture

A time base capture feature is provided as the PWM timer itself is not directly readable. When the timer value is needed, it may be captured and read via the PGxCAP register. There are two methods to capture a value: either manually with software or with hardware on a PCI event. The CAPSRC[2:0] control bits (PGxIOCON[30:28]) are used to select either a manual capture or one of the four PCI blocks as the trigger for a time base capture.

To manually capture the timer value, write a ‘1’ to PGxCAP[0]. The CAP status bit (PGxSTAT[5]) will set to indicate the capture is complete and then the user may read the PGxCAP register to determine the time base value at the time of the hardware event. A read operation of PGxCAP will clear the CAP status bit. No further captures are allowed until user software reads the PGxCAP register. Similarly, when a PCI block is used to capture a time base event, a read operation is needed to reset the logic to allow a subsequent capture event. It is recommended to read the CAP status bit to verify it is set before reading PGxCAP. This is to avoid a read of the PGxCAP register at the same time as the PWM hardware is writing it. An alternative method is to schedule reads with an interrupt to avoid concurrent access.

There will be up to four time base clock cycles of latency between the time of the actual event that caused the capture and the actual time base value that is captured. This delay is due to synchronization and sampling delays.