19.4.2.2 Slope Generation Mode

The slope generator function can be utilized in Peak Current-mode control-based power supply applications, where slope compensation is required. The slope function modifies the non-slope PDM DAC value repeatedly, at a user-defined rate, until the DAC data value reaches its endpoint. The slope generation function can be enabled or disabled by the SLOPEN bit (SLPxCON[31]). The slope rate is controlled by the data in the SLPxDAT register. The direction of slope being positive or negative is controlled by the PSE bit (SLPxCON[25]). For negative slopes (default, PSE = 0), DACDAT holds the nominal non-slope count, while DACLOW holds the count corresponding to the end of the slope. For positive slopes (PSE = 1), DACLOW holds the nominal non-slope count, while DACDAT holds the count corresponding to the end of the slope.

The slope generation start is controlled by the bits, SLPSTRT[3:0] (SLPxCON[3:0]). Depending on the value of SLPSTRT[3:0], the selected PWM trigger will be used to start the slope generation. The DAC output voltage changes to the value in DACDAT first by going to the Transition mode and then to the Steady-State mode. In Transition mode, the filter responds to new data values as fast as possible. The Transition mode duration is specified by the TMODTIME[9:0] bits (DACCTRL2[9:0]). The Transition mode duration, T_TR, is given by the equation:

T_TR = TMODTIME[9:0] * 2/F_DAC in Seconds

Where: F_DAC = DAC Frequency in Hz

The steady-state timer, specified by the SSTIME[9:0] bits, starts at the same time as the Transition mode timer. Once the Transition mode ends, the Steady-State mode starts, wherein the DAC output voltage settles to the new value. The Steady-State Time, T_SS, is calculated by the equation:

T_SS = SSTIME[9:0] * 2/F_DAC in Seconds

Note that the SSTIME[9:0] count should always be greater than the TMODTIME[9:0] count. At the end of the Steady-State mode, the DAC value settles at the new value and is ready for slope generation. The SLPSTRT[3:0] signal triggers the slope generation process.

Refer to the DAC electrical specifications for additional information on T_SS and T_TR values. These timing parameters can be additionally adjusted as needed for the application.

The slope generation is terminated when one of the two stop signals is asserted. The eight control register bits, SLPSTOPA[3:0] (SLPxCON[11:8]) and SLPSTOPB[3:0] (SLPxCON[7:4]), select the control signal to terminate the slope generation. The stop signals are logically ORed so that the slope is terminated when one of the trigger events materializes. In most power supply applications, SLPSTOPA[3:0] can be configured to terminate the slope at the end of the PWM cycle, while SLPSTOPB[3:0] can be configured to trigger when the current reaches a limit under a normal or Fault condition. It should be noted that the stop signal must terminate the slope at least T_SS (Steady-State Time) prior to the next PWM cycle start. This is necessary to allow the DAC value to reach and settle at the steady-state value, specified by DACDAT, before the next cycle begins.

The slope rate value to be specified in the SLPxDAT register depends on the start and end values of the slope specified by DACDAT and DACLOW, PWM time period, DAC clock frequency and the SSTIME[9:0] bits value. The SLPxDAT value can be determined by using the below equation.

Where:

DACDAT = DAC value at the start of slope

DACLOW = DAC value and the end of slope

T_{SLOPE_DURATION} = Slope duration time in seconds

T_DAC = 2/F_DAC in seconds