17.4.2.3.1 Complementary Output Mode

In Complementary Output mode, both the PWMxH and PWMxL signals are never active at the same time. A dead-time switching delay may be inserted between the two signals and is controlled by the PGxDT register. Complementary Output mode is selected when PMOD[1:0] (PGxIOCON[21:20]) = 00. For more information on dead time, see Dead Time.

Figure 17-13. PWMxH/PWMxL Rising and Falling Edges Due to Dead Time

Output Override Behavior in Complementary Output Mode

The PWMxH and PWMxL outputs may be controlled by external hardware signals or by software overrides. The output pins are restricted from being placed in a state which violates the complementary output relationship or in a state which violates dead-time insertion delays. An output pin may be driven inactive immediately as a result of a hardware event. However, a pin will not be driven active until the programmed dead-time delay has expired. The following hardware and software override states are programmed using the following:

PCI Fault event, FLTDAT[1:0] (PGxIOCON[7:6])
PCI current limit event, CLDAT[1:0] (PGxIOCON[5:4])
PCI feed-forward event, FFDAT[1:0] (PGxIOCON[3:2])
Debugger Halt, DBDAT[1:0] (PGxIOCON[1:0])
Software override, OVRENH (PGxIOCON[13]) and OVRENL (PGxIOCON[12])
Swap of PWMxH and PWMxL pins, SWAP (PGxIOCON[14])

Figure 17-14 shows the signal chain for override behavior in Complementary mode. The SWAP control is applied first and is therefore overridden by all other controls. Next, the request to drive a pin active is applied before dead time, so dead time is still applied to the output; after which, the dead-time generator is requested to drive a pin inactive. This arrangement allows the inactive state to take precedence over SWAP and an active request. Finally, the polarity control is applied to the pin.

The PCI overrides operate on a priority scheme; see Output Control PCI Blocks for more information.

Figure 17-14. Override and SWAP Signal Flow, Complementary Mode

Table 17-36 shows the rules for pin override conditions. The active state is a ‘1’ on the output pin and the inactive state is a ‘0’. An ‘x’ denotes a ‘don’t care’ input; ~PWM indicates the complementary output of the PWM Generator’s output.

Table 17-36. Override Behavior in Complementary Output Mode
Source	SWAP	OVRENH	OVRENL	OVRDAT[1:0]	FFDAT[1:0]	CLDAT[1:0]	FLTDAT[1:0]	DBGDAT[1:0]	PWMxH  Signal	PWMxL  Signal
Debug Override
DEBUG	`x`	`x`	`x`	`xx`	`xx`	`xx`	`xx`	`00`	Inactive	Inactive
								`01`	Inactive	Active
								`1x`	Active	Inactive
Fault Override – Debug Override must be Inactive
PCI FLT	`x`	`x`	`x`	`xx`	`xx`	`xx`	`00`	`xx`	Inactive	Inactive
							`01`		Inactive	Active
							`1x`		Active	Inactive
Current Limit Override – Fault and Debug Overrides must be Inactive
PCI CL	`x`	`x`	`x`	`xx`	`xx`	`00`	`xx`	`xx`	Inactive	Inactive
						`01`			Inactive	Active
						`1x`			Active	Inactive
Feed-Forward Override – Software, Current Limit, Fault and Debug Overrides must be Inactive
PCI FF	`x`	`0`	`0`	`xx`	`00`	`xx`	`xx`	`xx`	Inactive	Inactive
					`01`				Inactive	Active
					`1x`				Active	Inactive
Software Override – Current Limit, Fault and Debug Overrides must be Inactive
Software Override	`0`	`0`	`1`	`x0`	`xx`	`xx`	`xx`	`xx`	PWM	Inactive
	`0`	`1`	`0`	`0x`					Inactive	~PWM
	`1`	`0`	`0`	`00`					~PWM	PWM
		`0`	`1`	`x0`					~PWM	Inactive
		`0`	`1`	`x1`					Inactive	Active
	`x`	`1`	`0`	`1x`					Active	Inactive
		`1`	`1`	`00`					Inactive	Inactive
		`1`	`1`	`01`					Inactive	Active
		`1`	`1`	`1x`					Active	Inactive

Output Behavior At Start-Up in Complementary Mode

When the PWM is initialized and the ON bit is set, the outputs immediately go to a Complementary state. There is an output delay as the signals propagate through the PWM logic. This causes the start of the active duty cycle to appear delayed, with the PWMxL output transitioning to an Inactive state (pin high) for four master_pwm_clk cycles. Once active duty cycle starts, the PWMx pins will behave as stated in Table 17-36.