22.3.1 SPIx Control Register 1
- When AUDEN =
1, this module functions as if CKE =0, regardless of its actual value. - When FRMEN =
1, SSEN is not used. - MCLKEN can only be written when
the ON bit =
0. - This channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW.
- SPI operates with DMA in Standard Buffer mode only, ENHBUF =
0. - SPISGNEXT function is available for 8, 16 and 32-bit data length transfers only.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | SPIxCON1 |
| Offset: | 0x1800, 0x1820, 0x1840 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| AUDEN | SPISGNEXT | IGNROV | IGNTUR | AUDMONO | URDTEN | AUDMOD[1:0] | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FRMEN | FRMSYNC | FRMPOL | MSSEN | FRMSYPW | FRMCNT[2:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | DISSDO | MODE[32,16] | SMP | CKE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SSEN | CKP | MSTEN | DISSDI | DISSCK | MCLKEN | SPIFE | ENHBUF | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – AUDEN Audio Codec Support Enable bit(1)
| Value | Description |
|---|---|
1 |
Audio protocol is enabled; MSTEN controls the direction of
both SCKx and frame (a.k.a. LRC), and this module functions as if FRMEN =
|
0 |
Audio protocol is disabled |
Bit 30 – SPISGNEXT SPIx Sign-Extend RX FIFO Read Data Enable bit(6)
| Value | Description |
|---|---|
1 |
Data from RX FIFO is sign-extended (upper unused bits should replicate MSb of the received data) |
0 |
Data from RX FIFO is not sign-extended (upper unused bits are always 1’b0) |
Bit 29 – IGNROV Ignore Receive Overflow bit
| Value | Description |
|---|---|
1 |
A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO is not overwritten by the receive data |
0 |
A ROV is a critical error that stops SPI operation |
Bit 28 – IGNTUR Ignore Transmit Underrun bit
| Value | Description |
|---|---|
1 |
A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN is transmitted until the SPIxTXB is not empty |
0 |
A TUR is a critical error that stops SPI operation |
Bit 27 – AUDMONO Audio Data Format Transmit bit(2)
| Value | Description |
|---|---|
1 |
Audio data is mono (i.e., each data word is transmitted on both left and right channels) |
0 |
Audio data is stereo |
Bit 26 – URDTEN Transmit Underrun Data Enable bit(3)
| Value | Description |
|---|---|
1 |
Transmits data out of SPIxURDT register during Transmit Underrun conditions |
0 |
Transmits the last received data during Transmit Underrun conditions |
Bits 25:24 – AUDMOD[1:0] Audio Protocol Mode Selection bits(4)
| Value | Description |
|---|---|
11 |
PCM/DSP mode |
10 |
Right Justified mode: This module functions as if SPIFE =
|
01 |
Left Justified mode: This module functions as if SPIFE =
|
00 |
I2S mode: This module functions as if SPIFE =
|
Bit 23 – FRMEN Framed SPIx Support bit
| Value | Description |
|---|---|
1 |
Framed SPIx support is enabled (SSx pin is used as the FSYNC input/output) |
0 |
Framed SPIx support is disabled |
Bit 22 – FRMSYNC Frame Sync Pulse Direction Control bit
| Value | Description |
|---|---|
1 |
Frame Sync pulse input (client) |
0 |
Frame Sync pulse output (host) |
Bit 21 – FRMPOL Frame Sync/Client Select Polarity bit
| Value | Description |
|---|---|
1 |
Frame Sync pulse/Client Select is active-high |
0 |
Frame Sync pulse/Client Select is active-low |
Bit 20 – MSSEN Host Mode Client Select Enable bit
| Value | Description |
|---|---|
1 |
SPIx Client Select support is enabled with polarity determined by FRMPOL (SSx pin is automatically driven during transmission in Host mode) |
0 |
Client Select SPIx support is disabled (SSx pin will be controlled by port I/O) |
Bit 19 – FRMSYPW Frame Sync Pulse-Width bit
| Value | Description |
|---|---|
1 |
Frame Sync pulse is one serial word length wide (as defined by MODE[32,16]/WLENGTH[4:0]) |
0 |
Frame Sync pulse is one clock (SCKx) wide |
Bits 18:16 – FRMCNT[2:0] Frame Sync Pulse Counter bits
| Value | Description |
|---|---|
111 |
Reserved |
110 |
Reserved |
101 |
Generate/Receive a Frame Sync pulse on every 32 serial words |
100 |
Generate/Receive a Frame Sync pulse on every 16 serial words |
011 |
Generate/Receive a Frame Sync pulse on every 8 serial words |
010 |
Generate/Receive a Frame Sync pulse on every 4 serial words |
001 |
Generate/Receive a Frame Sync pulse on every 2 serial words (value used by audio protocols) |
000 |
Generate/Receive a Frame Sync pulse on each serial word |
Bit 15 – ON SPIx On bit
| Value | Description |
|---|---|
1 | Enables module |
0 | Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR modifications |
Bit 13 – SIDL SPIx Stop in Idle Mode bit
| Value | Description |
|---|---|
1 | Halts in CPU Idle mode |
0 | Continues to operate in CPU Idle mode |
Bit 12 – DISSDO Disable SDOx Output Port bit
| Value | Description |
|---|---|
1 | SDOx pin is not used by the module; pin is controlled by port function |
0 | SDOx pin is controlled by the module |
Bits 11:10 – MODE[32,16] Serial Word Length bits(1,4)
| MODE32 | MODE16 | AUDEN | Communication |
|---|---|---|---|
1 | x | 0 | 32-bit |
0 | 1 | 16-bit | |
0 | 0 | 8-bit | |
1 | 1 | 1 | 24-bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame |
1 | 0 | 32-bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame | |
0 | 1 | 16-bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame | |
0 | 0 | 16-bit FIFO, 16-Bit Channel/32-Bit Frame |
Bit 9 – SMP SPIx Data Input Sample Phase bit
Client Mode:
Input data is always sampled at the middle of data output time, regardless of the SMP setting.
Host Mode:
| Value | Description |
|---|---|
1 |
Input data is sampled at the end of data output time |
0 |
Input data is sampled at the middle of data output time |
Bit 8 – CKE SPIx Clock Edge Select bit(1)
| Value | Description |
|---|---|
1 | Transmit happens on transition from active clock state to Idle clock state |
0 | Transmit happens on transition from Idle clock state to active clock state |
Bit 7 – SSEN Client Select Enable bit (Client mode)(2)
| Value | Description |
|---|---|
1 | SSx pin is used by the module in Client mode; SSx pin is used as the Client Select input |
0 | SSx pin is not used by the module pin is controlled by port function |
Bit 6 – CKP Clock Polarity Select bit
| Value | Description |
|---|---|
1 | Idle state for clock is a high level; active state is a low level |
0 | Idle state for clock is a low level; active state is a high level |
Bit 5 – MSTEN Host Mode Enable bit
| Value | Description |
|---|---|
1 | Host mode |
0 | Client mode |
Bit 4 – DISSDI Disable SDIx Input Port bit
| Value | Description |
|---|---|
1 | SDIx pin is not used by the module; pin is controlled by port function |
0 | SDIx pin is controlled by the module |
Bit 3 – DISSCK Disable SCKx Output Port bit
| Value | Description |
|---|---|
1 | SCKx pin is not used by the module; pin is controlled by port function |
0 | SCKx pin is controlled by the module |
Bit 2 – MCLKEN SPI Host Clock Source Selection bit(3)
Bit 1 – SPIFE Frame Sync Pulse Edge Select bit
| Value | Description |
|---|---|
1 | Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock |
0 | Frame Sync pulse (Idle-to-active edge) precedes the first bit clock |
Bit 0 – ENHBUF Enhanced Buffer Enable bit(5)
| Value | Description |
|---|---|
1 | Enhanced Buffer mode is enabled |
0 | Enhanced Buffer mode is disabled |