29.4.9 Stopping the Sequencer

When the PTG module is disabled (ON = 0), the PTG clocks are disabled (except the trigger pulse counter), the sequencer stops execution and the module enters its lowest power state. The PTGSTRT, PTGSWT, PTGWDTO and PTGQPTR[4:0] bits are all reset. All other bits and registers are not modified. All of the control registers can be read or written when ON = 0.

When the ON bit is cleared, a command that is underway is immediately aborted if the command is waiting for any of the following actions:

An input from another source
A timer match
The step delay to expire (for more information, refer to Step Command Delay)

All other commands are allowed to complete before the PTG module is disabled.

When the PTG module is halted, all of the control registers remain in their present state. The PTG module can be halted by the user by clearing the PTGSTRT bit, or in the event of a Watchdog Timer time-out, which also clears the PTGSTRT bit. Refer to PTG Watchdog Timer for more information.

Note: If a command has triggered the pulse width delay counter, the counter is synchronously reset with respect to the PTG clock, terminating the pulse (subject to a minimum pulse width of 1 PTG clock cycle).