29.4.6.5 Step Command Delay

The Step Delay Timer (SDLY) is a convenient method to make each step command consume a specific amount of time. Normally, the user specifies a step delay equal to the duration of a peripheral function, such as the ADC conversion time. The step delay enables the user to generate the trigger output signals at a controlled rate, thereby avoiding overload on the target peripheral.

The PTGSDLIM register defines the additional time duration of each step command in terms of PTG clocks.

By default, the SDLY is disabled. The user can enable and disable the SDLY via the ‘PTGCTRL 0b0110’ or ‘PTGCTRL 0b0010’ command, which can be placed in the step queue.

When operating, the SDLY increments at the PTG clock rate. The PTGSDLIM register value is referred to as the step delay timer limit value. The step delay is inserted after each command is executed, so that all step commands are stalled until the PTGSD timer reaches its limit value. On reaching the limit value, the command execution completes and the next command starts execution. The timer is also cleared during execution of each command, so that it is ready for the next command execution.

The trigger sources for the edge-sensitive commands (‘PTGCTRL 0b1011’ and PTGWHI/PTGWLO when operated in Edge-Sensitive mode) have additional logic to recognize the appropriate edge transition. The edge detection logic is reset at the end of each command to maintain the edge-sensitive nature of these input triggers. If an additional valid edge occurs during a step delay that has been inserted after the step command has executed, it will not be recognized by any subsequent step command. Figure 29-9 explains the operation of the step command delay. As shown, step delay is inserted immediately following the PTGCTRL 0b0110 command which enables step delay, and is not inserted after the PTGCTRL 0b0010 command which disables step delay; the change is immediate.