1.3.2.5 CoreAXI4Interconnect IP
(Ask a Question)The CoreAXI4Interconnect IP is configured for the following initiator and target ports:
- Initiator0: PCIe
- Initiator1: CoreAXI4DMAController IP
- Initiator2: Pattern generator and checker logic (pattern_gen_checker block)
- Target0: AXItoAPB bridge (0x0000_0000 to 0x0FFF_FFFF)
- Target1: AXI Target Fabric Registers (0x1000_0000 to 0x1FFF_FFFF)
- Target2: DDR3L Subsystem (0x2000_0000 to 0x2FFF_FFFF) (not enabled for Splash kit)
- Target3: AXI4 LSRAM (0x3000_0000 to 0x3FFF_FFFF)
- Target4: DDR4 Subsystem (0x4000_0000 to 0x4FFF_FFFF)
Slave0 is configured to convert AXI4 transactions to AXI3 transactions.