40.12 FDPLL96M Electrical Specifications

Table 40-14. Frequency Digital Phase Locked Loop (FDPLL96M) AC Electrical Specifications
AC CHARACTERISTICSStandard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)

Operating temperature:

-40°C ≤ TA ≤ +125°C for Extended Temp

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
FDPLL96M (Fractional Digital Phase Locked Loop)
FDPLL_5FDPLL_Jitter(1,2) FDPLL96M Period Jitter Pk-to-Pk(1,2) 1.4—4.2%VDD = VDDIO = 5.0V,

fIN = 32.768 kHz from XOSC32K,

fOUT = 48 MHz

1—13.5%VDD = VDDIO = 5.0V,

fIN = 32.768 kHz from XOSC32K,

fOUT = 96 MHz

FDPLL_7 1.4—5%VDD = VDDIO = 5.0V,

fIN = 2 MHz from XOSC,

fOUT = 48 MHz

1—10.6%VDD = VDDIO = 5.0V,

fIN = 2 MHz from XOSC,

fOUT = 96 MHz

Note:
  1. REFCLK for FDPLL is XOSC or XOSC32K.
  2. DPLL jitter is sensitive to digital on-chip activity, which is application dependent.